Our goal is the development of a massively parallel hardware/software architecture for embedded systems, a "portable high-performance computing system for safety-critical applications". From the hardware point of view, the system will rely on a large number of interconnected processors on a so-called FPGA (Field Programmable Gate Array). The principle of each processor will be similar to that of today's RISC (Reduced Instruction Set) but has some novel features to conserve the scarce resources in an FPGA. From the software point of view, our model is designed to optimally support the mapping of parallelism in algorithms to the parallelism in our hardware. Mathematical algorithms are then executed utilizing as many of our CPUs as available. A high-performance health monitoring application will serve as a proof of concept: an ultrasound-based heart monitor is to automatically detect anomalies in the blood flow and movement of the heart. The necessary complex mathematical algorithms require a sufficiently abstract programming model. Their execution in an acceptable time frame demands high computing power made possible by a high degree of parallelization.
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