Recommendations for AGP 3.x Capability Register Design

This article provides information for hardware engineers about how to design AGP 3.x chipsets for the Microsoft Windows family of operating systems. Microsoft recommends that all AGP 3.x chipsets designed to be used with multiple AGP buses place the AGP capability registers in the PCI-to-PCI bridge.

Under most existing implementations of AGP 3.0, the AGP capability registers that control the PCI-to-PCI bridges are located in the host-to-PCI bridge. As a result, each AGP bus contains an implicit dependency upon the host-to-PCI bridge. If multiple AGP buses are present in the system, configuring each PCI-to-PCI bridge is difficult because the PCI driver must query the appropriate set of registers, all of which are contained in the host-to-PCI bridge.

However, if chipsets that support multiple PCI-to-PCI bridges place the AGP capability registers directly on the PCI-to-PCI bridges, it is easier for the PCI driver to associate the proper set of registers with the bridge they control. Also, there is an explicit interface between the AGP bus and the PCI-to-PCI bridge that supports it. The capabilities list bit in the PCI-to-PCI status register should be set and the AGP capability structure must be included in the capabilities list.

The recommended AGP 3.x chipset design is detailed in the diagram below, which shows two AGP buses and the root PCI bus. The dotted lines represent the most current implementations, where the AGP bus is dependent on the host-to-PCI bridge. The solid lines represent the proposed interface between the AGP bus and the PCI-to-PCI bridge, which contains the AGP capability registers.

Call to Action:
Hardware engineers should redesign their AGP 3.x implementations to meet the guidelines described in this article. Chipsets that support multiple PCI-to-PCI bridges should place the AGP capability registers directly on the PCI-to-PCI bridges.

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