Memory Barriers on Multiprocessor Architectures
The code you write is not necessarily executed in the order in which the instructions appear in the source.
Optimizing compilers, such as the Microsoft C compiler, sometimes eliminate or reorder read and write instructions if the optimizations do not break the logic of the routine being compiled. In addition, certain hardware architectures sometimes reorder read and write instructions to improve performance. Furthermore, on multiprocessor architectures, the sequence in which read and write operations are executed can appear different from the perspective of different processors.
Most of the time, reordering by the compiler or the hardware is completely invisible and has no effect on results other than generating them more efficiently. However, in a few situations, you must prevent or control reordering. The volatile keyword in C and the Windows synchronization mechanisms can ensure program order of execution in nearly all situations. In some rare instances, the executable code must contain memory barriers to prevent hardware reordering.
Complete information about compiler and hardware reordering and the use of memory barriers is now available in Multiprocessor Considerations for Kernel-Mode Drivers. This information expands on the information previously available in the paper "Memory Barriers in Kernel-Mode Drivers."
