Technologies such as systems-on-chip (SoCs), distributed switching fabrics, silicon photonics, and programmable hardware are enabling high density designs with very high bandwidth and low latency communication at the scale of a rack. In the near future, we expect to see “rack-scale computers” with 1,000s of cores and terabytes of memory, connected with bandwidth and latency comparable to today’s smaller-scale NUMA servers. These architectures are being driven by the need to increase density and connectivity between servers while lowering cost and power consumption. Early examples of these platforms have already appeared on the market from manufactures such as AMD SeaMicro, HP, and Intel and similar solutions are being deployed at large-scale companies such as Facebook and Microsoft.
These new architectures challenge traditional assumptions and raise several interesting research questions. For example, should we think of these rack-scale units as shared-memory machines, as distributed systems, or both? What is the interconnect topology for a rack-scale computer? Which parts of the communication stack should be implemented in hardware versus software? What are the correct failure models and fault-tolerant designs? How should we integrate rack-scale computers into data center networks? What new tools are needed to assist system designers? How can researchers effectively prototype and test novel ideas in this space?
The goal of this workshop is to bring together researchers and practitioners spanning the hardware, networking, storage, systems, and application domains, to discuss innovative designs and implementations for these new architectures.