Computer Architecture Group

Established: November 16, 2006

Our group’s mission is to conduct fundamental research in computer architecture and hardware/software interaction. We explore novel architectural techniques to improve the performance, efficiency, dependability, and scalability of processor architectures and the software running on them. We are especially interested in understanding and improving the interactions between hardware and software.









Pocket Cloudlets
Emmanouil Koukoumidis, Dimitrios Lymberopoulos, Karin Strauss, Jie Liu, Doug Burger, in ASPLOS 2011 (International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, March 1, 2011, View abstract, Download PDF



An Evaluation of the TRIPS Computer System
Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeff Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James Burrill, Stephen W. Keckler, Doug Burger, Kathryn S McKinley, in International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, March 7, 2009, View abstract, View external link





HPCA-17 and Microsoft Research

Austin, TX, USA | February 2017

Microsoft Research is a Silver sponsor of the 23rd IEEE Symposium on High Performance Computer Architecture (HPCA) at the Austin Hilton in Austin, TX, February 4-8, 2017.


Compression Accelerators

Established: June 16, 2014

Data compression is essential to large-scale data centers to save both storage and network bandwidth. Current software based method suffers from high computational cost with limited performance. In this project, we are migrating the fundamental workload of the computer system to FPGA accelerator, aiming high throughput performance and high energy efficiency, as well as freeing some CPU resources. Target algorithm Xpress Compression Algorithm is Microsoft compression format that combines the dictionary based LZ77 method…


Achieving the right balance of power and performance for an application is challenging with today's multicore processors. E2 solves this problem by providing the capability for cores to dynamically adapt their resources during execution to provide highly efficient power/performance hardware configurations for a wide range of workloads. Explicit Data Graph Execution At the heart of E2 is an advanced Explicit Data Graph Execution (EDGE) instruction set architecture (ISA), which unlike conventional ISAs: Encodes the data dependencies between…


Established: February 26, 2008

The BEE3 (Berkeley Emulation Engine, version 3) is a multi-FPGA system with up to 64 GB of DRAM and several I/O subsystems that can be used to enable faster, larger and higher fidelity computer architecture or other systems research. Objective: Revitalizing Computer Architecture Research The Problem Computer Architecture is increasingly incremental, and boring. Many papers study a tiny feature, and report 5% improvements. Simulation is too slow to allow full-system experiments running real…

Microsoft Research blog

Energy-Efficiency Work Reaps Rewards

By Rob Knies, Managing Editor, Microsoft Research These days, more than ever, it’s important for computing to be energy-efficient. Particularly in data centers, energy requirements represent a significant portion of operational costs, and power and cooling needs help dictate where data centers can be located, how close to capacity they can operate, and how robust they are to failure. In part, however, this is true because computers are precision machines. They’re hard-wired that way. Ask…

August 2009

Microsoft Research Blog