About

Professional Activities

  • Workshops and Tutorials Chair, ACM Conference on Programming Language Design and Implementation (PLDI), 2017, 2018
  • Sponsorship Chair, IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2018
  • PC Chair, IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2017
  • Sponsorship Chair, ACM Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2017
  • External Reviewer, IEEE/ACM International Symposium on Microarchitecture (MICRO), 2013, 2015, 2016
  • PC Member, IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2014, 2016
  • PC Member, IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2015
  • General Chair, IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2015
  • External Reviewer, IEEE/ACM International Symposium on Computer Architecture (ISCA), 2015
  • External Reviewer, IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2015
  • PC Member, Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT), 2015
  • External Reviewer, ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, 2015
  • PC Member, Workshop on Adaptive Self-tuning Computing Systems (ADAPT), 2014, 2015, 2016
  • Session Chair, IEEE Symposium on Performance Analysis of Systems and Software (ISPASS), 2014, 2015
  • PC Member, IEEE Symposium on Parallel and Distributed Processing with Applications (ISPA), 2014
  • External Reviewer, IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012
  • PC Member, International Workshop On Cyber-Physical Systems, Networks, and Applications, 2011, 2012

Projects

E2

Achieving the right balance of power and performance for an application is challenging with today's multicore processors. E2 solves this problem by providing the capability for cores to dynamically adapt their resources during execution to provide highly efficient power/performance hardware configurations for a wide range of workloads. Explicit Data Graph Execution At the heart of E2 is an advanced Explicit Data Graph Execution (EDGE) instruction set architecture (ISA), which unlike conventional ISAs: Encodes the data dependencies between…

Publications

2017

2016

2015

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services (IEEE MICRO Top Pick)
Andrew Putnam, Adrian Caulfield, Eric Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Gopi Prashanth Gopal, Jan Gray, Michael Haselman, Scott Hauck, Stephen Heil, Amir Hormati, Joo-Young Kim, Sitaram Lanka, James Larus, Eric Peterson, Simon Pope, Aaron Smith, Jason Thong, Phillip Yi Xiao, Doug Burger, in IEEE Micro, IEEE, May 13, 2015, View abstract, Download PDF, View external link

2014

2013

2010

2009

An Evaluation of the TRIPS Computer System
Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeff Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James Burrill, Stephen W. Keckler, Doug Burger, Kathryn S McKinley, in International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), ACM, March 7, 2009, View abstract, View external link

2008

2007

2006

Dataflow Predication
Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert McDonald, Doug Burger, Stephen W. Keckler, Kathryn McKinley, in 39th International Symposium on Microarchitecture (MICRO), IEEE/ACM, December 1, 2006, View abstract, Download PDF