A former member of the ACME Lab at the University of Washington, Ken completed his Ph.D. in Electrical Engineering in 2008. His dissertation discussed the fundamental problems that heavily pipelined applications pose to conventional FPGA architectures and physical design tools. He investigated new CAD algorithms and FPGA architectures that could accomodate the deeply pipelined netlists required for today’s high-throughput applications. His only dissertation-claim-to-fame? Apparently the issues he was trying to address weren’t completely imaginary. Announced in mid-2009 and mid 2010 respectively, the new Xilinx Virtex-6 and Altera Stratix V architectures both have double the number of registers per logic block compared with previous generation devices.
Ken joined the Embedded and Reconfigurable Computing Group in 2008 and is an Affiliate Assistant Professor in the Electrical Engineering Department at the University of Washington. Some of his past & present research interests include:
Innovative high-performance computing architectures
Applications of reconfigurable computing platforms
Addressing FPGA development difficulties and system integration / interfacing issues
Security concerns & advantages of hardware accelerators
Cryptography & cryptanalysis