I’m a Senior Researcher at MSR-NExT, working on hardware accelerator technologies and deep learning. I’ve been a core member of the Microsoft Catapult project since its early days and contributed to the research, piloting, and production deployment of FPGAs at hyperscale (see Wired article). Today, Catapult FPGAs are being integrated into every new server deployed in Microsoft’s datacenters and play a crucial role in accelerating critical AI scenarios within Bing and enabling ultra-low latency and high-bandwidth networking within Azure.
As a technical and research lead, I work on identifying opportunities for harnessing post-CPU technologies in potentially disruptive ways (e.g., deep learning), planning and design of future generation platforms, and partnering with other product and research teams on high-valued scenarios. As a hardware engineer, I have also contributed to foundational infrastructure for Catapult and continue to support production demands.
My broader research interests are in computer architecture, reconfigurable computing, datacenter and cloud, hardware-accelerated machine learning, domain-specific high-level synthesis, FPGA-based simulation methodologies, heterogeneous multicore analytical modeling, and hardware design automation.
I have served as a reviewer, program committee member, and general committee member for major conferences, including ASPLOS, ISCA, MICRO, HPCA, FPGA, and FCCM. I received my Ph.D. at Carnegie Mellon University in 2011 and a B.S. from UC Berkeley in EECS in 2004. Previously, I led the CoRAM and ProtoFlex projects at CMU.