Portrait of Eric Chung

Eric Chung

Researcher

About

I’m a researcher at MSR-NExT, working on post-CPU technologies and deep learning. I’ve been a core member of the Microsoft Catapult project since its early days and contributed to the research, piloting, and production deployment of FPGAs at hyperscale (see Wired article). Today, Catapult FPGAs are being integrated into every new server deployed in Microsoft’s datacenters and play a crucial role in accelerating critical AI scenarios within Bing and enabling ultra-low latency and high-bandwidth networking within Azure.

As a technical and research lead, I work on identifying opportunities for harnessing post-CPU technologies in potentially disruptive ways (e.g., deep learning), planning and design of future generation platforms, and partnering with other product and research teams on high-valued scenarios. As a hardware engineer, I have also contributed to foundational infrastructure for Catapult and continue to support production demands.

My broader research interests are in computer architecture, reconfigurable computing, datacenter and cloud, hardware-accelerated machine learning, domain-specific high-level synthesis, FPGA-based simulation methodologies, heterogeneous multicore analytical modeling, and hardware design automation.

I have served as a reviewer, program committee member, and general committee member for major conferences, including ASPLOS, ISCA, MICRO, HPCA, FPGA, and FCCM. I received my Ph.D. at Carnegie Mellon University in 2011 and a B.S. from UC Berkeley in EECS in 2004. Previously, I led the CoRAM and ProtoFlex projects at CMU.

Projects

Project Catapult

Established: June 1, 2011

Project Catapult is the technology behind Microsoft’s hyperscale acceleration fabric, and is at the center of a comprehensive set of investments Microsoft is making to build a supercomputing substrate that can accelerate our efforts in networking, security, cloud services and…

Publications

2015

2014

Other

CV

Service

  • Program committees – ASBD’14, FCCM’14, SBAC-PAD’14, CARL’13, FCCM’13, FCCM’12
  • External committees – MICRO’14, MICRO’12
  • External reviewer – MICRO, HPCA, ASPLOS, FCCM, TRETS, CARL, CASES, HIPEAC, TPDS
  • Publications Chair – ISCA’14

Contributions

Selected Publications

Selected Talks and Tutorials

  • RAMP Simulator Tutorial: Protoflex, FAST, HAsim, and RAMP-GoldHeld in conjunction with ISPASS-2010, March 28, 2010.
  • Open Source Protoflex SimulatorRAMP summer retreat at UT Austin, Austin, TX, 6/09.
  • Accelerating Architectural-Level Full-System Simulations Using FPGAsGuest speaker at Microsoft Research, Redmond, CA, 10/07.
  • Architectural Emulation on FPGAs Made Easy with Bluespec1st Bluespec Workshop at MIT, Boston, MA, 8/07.
  • Combining Simulators and FPGAs: “An Out-of-Body Experience”RAMP summer retreat at MIT, Boston, MA, 6/06.