Achieving the right balance of power and performance for an application is challenging with today’s multicore processors. E2 solves this problem by providing the capability for cores to dynamically adapt their resources during execution to provide highly efficient power/performance hardware configurations for a wide range of workloads.
Explicit Data Graph Execution
At the heart of E2 is an advanced Explicit Data Graph Execution (EDGE) instruction set architecture (ISA), which unlike conventional ISAs:
- Encodes the data dependencies between instructions, freeing the microarchitecture from rediscovering these dependencies at runtime, and
- Groups instructions into atomic blocks (similar to transactions), providing a larger unit of work, and allowing the microarchitecture to tolerate growing wire delays
These two ISA features enable E2 to utilize a dataflow execution model, providing power-efficient out-of-order execution.
|Current multicore systems provide a fixed and rigid computational substrate. In E2, physical cores are dynamically composable into powerful logical processors, allowing a single chip to tailor itself to the computational needs of a wide range workloads. E2 is configurable to provide:
- Many physical cores working independently,
- Many physical cores working in parallel to perform the same operations on multiple data sets simultaneously,
- Many physical cores composed together to form logical processors to accelerate single-threads of execution.
Core fusion allows E2 to span a wide power/performance spectrum, from power-efficient embedded processors to high-performance server class processors.