This paper explores the idea of using regular parallelism and concurrency constructs in mainstream languages for the description, implementation and verification of digital
circuits. We describe the Kiwi parallel programming library and its associated synthesis system which is used to transform parallel programs into circuits for realization
on FPGAs. Although there has been much work on compiling sequential C-like programs to hardware by automatically discovering parallelism, we work by exploiting
the parallel architecture communicated by the designer through the choice of parallel and concurrent programming language constructs. In particular, we describe a
system that takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. We can then choose to apply analysis and verification techniques to either the highlevel representation in C# or other .NET languages or to the generated RTL netlists. For example, we show how a parallel combinator style description can be used to describe a parallel sorting network in F#. A distinctive aspect of our approach is the exploitation of existing language constructs for concurrent programming and synchronization which contrasts with other schemes which
introduce specialized concurrency control constructs to extend a sequential language. One of our aims is to be able to deploy formal analysis techniques developed for
parallel programs to the verification of digital circuits represented as parallel programs.