Extending gNOSIS for System Verilog HDL Static Analysis
Software engineering tools for Hardware Design Languages (HDL) lag behind traditional software development tools by decades. However as heterogeneous computing becomes more pervasive, productive programming in HDLs will become vital. To this end, we have developed gNOSIS a static analysis platform for Verilog HDL. In this project we have extended gNOSIS to support System Verilog. A good analogy is C is to C++ as Verilog is to System Verilog, that is System Verilog is a superset of Verilog with more sophisticated features. This report details the challenges, approach, and progress we’ve made towards supporting System Verilog in gNOSIS.