Technology forecasts indicate that device scaling will continue well into the next decade.
Unfortunately, it is becoming extremely difficult to harness performance out of such an abundance of transistors due to a number of technological, circuit, architectural, methodological and programming challenges. In this talk, I will argue that the ultimate emerging showstopper is power even for workloads abound in parallelism. Voltage scaling as a means to maintain a constant power envelope with an increase in transistor numbers has hit diminishing returns, requiring drastic measures to cut power to continue riding the Moore’s law. I will present results backing this argument based on validated models for future server chips and parameters extracted from real commercial workloads. Then I use these results to project future research directions for server hardware and software.