Embedded systems are often subject to real-time constraints. Such systems require determinism to ensure that task deadlines are met. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines. Knowledge of bounds on worst-case execution times (WCET) of tasks is a critical piece of information required by schedulability analysis. Static timing analysis derives these bounds on WCETs, but requires that bounds on loop iterations be known statically, i.e., at compile time. This often limits the class of applications that may be analyzed by static timing analysis and, hence, used in a real-time system. Another limiting factor for real-time system design is the class of processors that may be used. Typically, modern, complex, processors may not be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, and prefetching, cannot be statically analyzed to obtain WCETs for tasks. The main reason is that these features introduce non-determinism to task execution, which can only be resolved at run-time.
The contributions of this work are two-fold. First, we show how the constraint concerning statically bound loops may be relaxed and applied to make dynamic decisions at run-time to obtain power savings. Second, we introduce a new paradigm, which proposes minor enhancements to modern processor architectures, which, on interaction with software modules, is able to obtain tight, accurate timing analysis results for modern processors.
To the best of our knowledge, these methods of (a) using run-time information to obtain accurate upper bounds for loops and using that information to achieve energy savings, and (b) hardware/software interactions to calculate WCET results for out-of-order processors, are the first of their kind.