If you have a research project that can benefit from\u00a0programmable hardware, and high speed, powerful computational performance, you can request access to the Microsoft Project Catapult<\/a> system at the TACC\u00a0by following the instructions\u00a0on the Apply tab and\u00a0sending a one-page proposal to\u00a0catapult@microsoft.com<\/a>.<\/p>\n Join the Catapult Academic mailing list (opens in new tab)<\/span><\/a>to keep updated<\/p>\n The Project Catapult Academic Program allows researchers worldwide to investigate new ways of using interconnected FPGAs as computational accelerators\u2014a unique opportunity to access custom data center systems for high-demand research. Using the low-latency Catapult system opens up opportunities to create innovative applications and run high-demand research applications\u2014such as machine learning and deep learning algorithms\u2014at previously unavailable efficiencies and scale.<\/p>\n The Project Catapult Academic Program is run in collaboration with the\u00a0Texas Advanced Computing Center (opens in new tab)<\/span><\/a> (TACC) at The University of Texas at Austin, and Intel (opens in new tab)<\/span><\/a>. It provides researchers with free access to Microsoft Catapult FPGA systems located at TACC, including 384 Catapult nodes at TACC, and a Catapult shell development kit, tools, and examples for researchers to develop their own FPGA applications to run on the Catapult FAbRIC platform.<\/p>\n Researchers can request access to the Microsoft Project Catapult system at the TACC\u00a0by following the instructions\u00a0on the Apply tab and\u00a0sending a one-page proposal to\u00a0catapult@microsoft.com<\/a>.<\/p>\n General questions regarding Project Catapult Academic Program may be sent to catapult@microsoft.com<\/a><\/p>\n Keep updated via the Catapult mailing list (opens in new tab)<\/span><\/a><\/p>\n All of the code that I will pass through FAbRIC CAD tools (such as Verilog files, Bluespec files, etc.) and the files needed to process that code (such as Makefiles) is either already open source (GPL version 2 or above, BSD, or MIT licenses) or I have the right to make it open source and am hereby making all of the code that I pass through FAbRIC CAD tools open source by one of those licenses. I will provide access to my source code to the CAD tool vendors and the FAbRIC administrators immediately. The simplest way to do that is to provide a repository account to the FAbRIC administrators. By default, the CAD tool vendors and\/or the FAbRIC administrators agree not to publish the code publicly for at least 12 months.<\/em><\/p>\n I acknowledge that the tools, servers, and FPGAs are potentially subject to export controls under U.S. and other applicable government laws and regulations. I will comply with these laws and regulations and agree to obtain all required government authorizations.<\/em><\/p>\n I acknowledge that my access to and use of the Microsoft Project Catapult Academic Shell and Driver and related hardware provided by Microsoft is governed by, and subject to, the terms and conditions of the Microsoft Research License Agreement for the<\/em>\u00a0Microsoft Project Catapult Academic Shell and Driver<\/em><\/a>. By accessing or using Microsoft Project Catapult materials, I represent and warrant that I have read the agreement, and I agree to be bound by it.<\/em><\/p>\n The system consists of 384 2-socket Intel Xeon-based nodes, each with 64 GB of RAM and an Altera Stratix V FPGA with 8 GB of local DDR3 SDRAM. FPGAs communicate to their host CPUs via a PCIe Gen3 x8 connection, providing 8 GB\/s guaranteed-not-to-exceed bandwidth, and each FPGA can read and write data stored on its host node using this connection.<\/p>\n The FPGAs are connected to one another via a dedicated network using high-speed serial links. This network, called CatNet (Catapult Network), forms a two-dimensional torus within a pod of 48 servers and provides low-latency communication between neighboring FPGAs. This design supports the use of multiple FPGAs to solve a single problem\u00a0while adding resilience to server and FPGA failures.<\/p>\n Per Node:<\/p>\n\n
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