The Problem<\/h2>\n\n- Computer Architecture is increasingly incremental, and boring.<\/li>\n
- Many papers study a tiny feature, and report 5% improvements.<\/li>\n
- Simulation is too slow to allow full-system experiments running real software.<\/li>\n
- Researchers can no longer build real chips to test new ideas \u2013 it\u2019s too expensive.<\/li>\n<\/ul>\n
Our Goal: Change this<\/h2>\n\n- Provide an experimental platform for the research community.<\/li>\n<\/ul>\n
The Solution: BEE3<\/h2>\n
BEE3 stands for the Berkeley Emulation Engine version 3. The BEE3 system is a 2U chassis with a tightly-couple 4 FPGA system that is a vehicle for Computer Architecture Research. In particular, the BEE3 is the target platform for the Research Accelerator for Multiple Processors (RAMP (opens in new tab)<\/span><\/a>). RAMP is a collection of six universities (Berkeley, Stanford, UW, UT, CMU, and MIT) and several industry partners including: Microsoft Research, Xilinx, Sun Microsystems and IBM. The BEE3 is a scalable platform, 1 to 64 2U systems, that facilitates research in a multiple areas: Computer Architecture, Systems, OS and Software, Memory Hierarchy and Storage, and various Application\/Algorithm Accelerators, to name a few.<\/p>\n\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t\tExpand all\t\t\t\t\t<\/button>\n\t\t\t\t\t | <\/span>\n\t\t\t\t\t\n\t\t\t\t\t\tCollapse all\t\t\t\t\t<\/button>\n\t\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\t\t\t\t- \n\t\t\n\t\t\t
\n\t\t\t\tImportant BEE3 details\t\t\t<\/button>\n\t\t<\/div>\n\t\t\n\t\t\t\n\t\t\t\tThe BEE3 design has been licensed to BEEcube<\/b> (opens in new tab)<\/span><\/a>. (opens in new tab)<\/span><\/a> Please contact BEEcube for product ordering and pricing information.<\/p>\nThe BEE3 DDR2 controller is available at the Microsoft Research downloads repository. You can also search for the controller by name: “DDR2 DRAM Controller for BEE3”.<\/p>\n
The pictures below show the rack mounted 2U BEE3 system and the inside of the 2U system with the major components labeled.<\/p>\n
![\"\"](\"https:\/\/www.microsoft.com\/en-us\/research\/wp-content\/uploads\/2016\/02\/bee3-image002.jpg\")
<\/span><\/span>![\"\"](\"https:\/\/www.microsoft.com\/en-us\/research\/wp-content\/uploads\/2016\/02\/bee3-image004.jpg\")
<\/span><\/span><\/p>\nThe BEE3 system is made up of a Main<\/b> Printed Circuit Board (PCB) and a Control & I\/O<\/b> PCB with the following components:<\/p>\n\n- 2U Enclosure with standard PC components\n
\n- Fans, power supply, etc.<\/li>\n<\/ul>\n<\/li>\n
- BEE3 Main PCB<\/li>\n
- 4 Xilinx FPGAs (FF1136 package)\n
\n- Virtex-5 LX110T, LX155T, or SX95T<\/li>\n<\/ul>\n<\/li>\n
- 16 DDR2 DIMMs\n
\n- 2 DDR2 (400) channels per FPGA<\/li>\n
- Up to two 4 GB DIMMs per channel<\/li>\n<\/ul>\n<\/li>\n
- FPGA Ring Interconnect<\/li>\n
- 8 10 GBase-CX4 Interfaces<\/li>\n
- 4 PCI-Express slots (endpoint only)<\/li>\n
- 4 QSH-DP (40 LVDS pairs) Connectors<\/li>\n
- 4 1GbE RJ45 Ports<\/li>\n<\/ul>\n
\n- BEE3 Control & I\/O PCB\n
\n- 4 RS232 via RJ45 Connectors<\/li>\n
- 4 SD Slots\n
\n- Per FPGA Persistent Storage<\/li>\n<\/ul>\n<\/li>\n
- 1 Compact Flash slot and System Ace support\n
\n- FPGA Configuration Storage (Bit Files)<\/li>\n<\/ul>\n<\/li>\n
- 1 Xilinx USB-JTAG Interface<\/li>\n
- 2 SMA Clock Inputs<\/li>\n
- Power Switch<\/li>\n
- Global Reset Button<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
The BEE3 Main PCB connectivity is shown in the diagram below:<\/p>\n
![\"\"](\"https:\/\/www.microsoft.com\/en-us\/research\/wp-content\/uploads\/2016\/02\/bee3-image008.gif\")
<\/span><\/span><\/p>\n\t\t\t<\/div>\n\t\t<\/div>\n\t<\/li>\n\t\t- \n\t\t\n\t\t\t
\n\t\t\t\tTalks\t\t\t<\/button>\n\t\t<\/div>\n\t\t\n\t\t\t\n\t\t\t\t\n- RAMP BEE3 Updated January 2007 <\/a><\/li>\n
- RAMP BEE3 Updated June 2007<\/a><\/li>\n
- RAMP BEE3 Updated January 2008<\/a><\/li>\n
- RAMP BEE3 Wrap up June 2010<\/a><\/li>\n<\/ul>\n\t\t\t<\/div>\n\t\t<\/div>\n\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t<\/div>\n\t\n","protected":false},"excerpt":{"rendered":"
The BEE3 (Berkeley Emulation Engine, version 3) is a multi-FPGA system with up to 64 GB of DRAM and several I\/O subsystems that can be used to enable faster, larger and higher fidelity computer architecture or other systems research. Objective: Revitalizing Computer Architecture Research The Problem Computer Architecture is increasingly incremental, and boring. Many papers […]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","footnotes":""},"research-area":[13552,13547],"msr-locale":[268875],"msr-impact-theme":[],"msr-pillar":[],"class_list":["post-169466","msr-project","type-msr-project","status-publish","hentry","msr-research-area-hardware-devices","msr-research-area-systems-and-networking","msr-locale-en_us","msr-archive-status-active"],"msr_project_start":"2008-02-26","related-publications":[145451,153745,157368,159453,160486],"related-downloads":[],"related-videos":[],"related-groups":[],"related-events":[],"related-opportunities":[],"related-posts":[],"related-articles":[],"tab-content":[],"slides":[],"related-researchers":[{"type":"user_nicename","value":"cthacker","display_name":"Chuck Thacker","author_link":"Chuck Thacker<\/a>","is_active":false,"user_id":31483,"last_first":"Thacker, Chuck","people_section":0,"alias":"cthacker"}],"msr_research_lab":[],"msr_impact_theme":[],"_links":{"self":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project"}],"about":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/types\/msr-project"}],"version-history":[{"count":1,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466\/revisions"}],"predecessor-version":[{"id":215845,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466\/revisions\/215845"}],"wp:attachment":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/media?parent=169466"}],"wp:term":[{"taxonomy":"msr-research-area","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/research-area?post=169466"},{"taxonomy":"msr-locale","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-locale?post=169466"},{"taxonomy":"msr-impact-theme","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-impact-theme?post=169466"},{"taxonomy":"msr-pillar","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-pillar?post=169466"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
Our Goal: Change this<\/h2>\n\n- Provide an experimental platform for the research community.<\/li>\n<\/ul>\n
The Solution: BEE3<\/h2>\n
BEE3 stands for the Berkeley Emulation Engine version 3. The BEE3 system is a 2U chassis with a tightly-couple 4 FPGA system that is a vehicle for Computer Architecture Research. In particular, the BEE3 is the target platform for the Research Accelerator for Multiple Processors (RAMP (opens in new tab)<\/span><\/a>). RAMP is a collection of six universities (Berkeley, Stanford, UW, UT, CMU, and MIT) and several industry partners including: Microsoft Research, Xilinx, Sun Microsystems and IBM. The BEE3 is a scalable platform, 1 to 64 2U systems, that facilitates research in a multiple areas: Computer Architecture, Systems, OS and Software, Memory Hierarchy and Storage, and various Application\/Algorithm Accelerators, to name a few.<\/p>\n\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t\tExpand all\t\t\t\t\t<\/button>\n\t\t\t\t\t | <\/span>\n\t\t\t\t\t\n\t\t\t\t\t\tCollapse all\t\t\t\t\t<\/button>\n\t\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\t\t\t\t- \n\t\t\n\t\t\t
\n\t\t\t\tImportant BEE3 details\t\t\t<\/button>\n\t\t<\/div>\n\t\t\n\t\t\t\n\t\t\t\tThe BEE3 design has been licensed to BEEcube<\/b> (opens in new tab)<\/span><\/a>. (opens in new tab)<\/span><\/a> Please contact BEEcube for product ordering and pricing information.<\/p>\nThe BEE3 DDR2 controller is available at the Microsoft Research downloads repository. You can also search for the controller by name: “DDR2 DRAM Controller for BEE3”.<\/p>\n
The pictures below show the rack mounted 2U BEE3 system and the inside of the 2U system with the major components labeled.<\/p>\n
<\/span><\/span><\/span><\/span><\/p>\nThe BEE3 system is made up of a Main<\/b> Printed Circuit Board (PCB) and a Control & I\/O<\/b> PCB with the following components:<\/p>\n\n- 2U Enclosure with standard PC components\n
\n- Fans, power supply, etc.<\/li>\n<\/ul>\n<\/li>\n
- BEE3 Main PCB<\/li>\n
- 4 Xilinx FPGAs (FF1136 package)\n
\n- Virtex-5 LX110T, LX155T, or SX95T<\/li>\n<\/ul>\n<\/li>\n
- 16 DDR2 DIMMs\n
\n- 2 DDR2 (400) channels per FPGA<\/li>\n
- Up to two 4 GB DIMMs per channel<\/li>\n<\/ul>\n<\/li>\n
- FPGA Ring Interconnect<\/li>\n
- 8 10 GBase-CX4 Interfaces<\/li>\n
- 4 PCI-Express slots (endpoint only)<\/li>\n
- 4 QSH-DP (40 LVDS pairs) Connectors<\/li>\n
- 4 1GbE RJ45 Ports<\/li>\n<\/ul>\n
\n- BEE3 Control & I\/O PCB\n
\n- 4 RS232 via RJ45 Connectors<\/li>\n
- 4 SD Slots\n
\n- Per FPGA Persistent Storage<\/li>\n<\/ul>\n<\/li>\n
- 1 Compact Flash slot and System Ace support\n
\n- FPGA Configuration Storage (Bit Files)<\/li>\n<\/ul>\n<\/li>\n
- 1 Xilinx USB-JTAG Interface<\/li>\n
- 2 SMA Clock Inputs<\/li>\n
- Power Switch<\/li>\n
- Global Reset Button<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
The BEE3 Main PCB connectivity is shown in the diagram below:<\/p>\n
<\/span><\/span><\/p>\n\t\t\t<\/div>\n\t\t<\/div>\n\t<\/li>\n\t\t- \n\t\t\n\t\t\t
\n\t\t\t\tTalks\t\t\t<\/button>\n\t\t<\/div>\n\t\t\n\t\t\t\n\t\t\t\t\n- RAMP BEE3 Updated January 2007 <\/a><\/li>\n
- RAMP BEE3 Updated June 2007<\/a><\/li>\n
- RAMP BEE3 Updated January 2008<\/a><\/li>\n
- RAMP BEE3 Wrap up June 2010<\/a><\/li>\n<\/ul>\n\t\t\t<\/div>\n\t\t<\/div>\n\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t<\/div>\n\t\n","protected":false},"excerpt":{"rendered":"
The BEE3 (Berkeley Emulation Engine, version 3) is a multi-FPGA system with up to 64 GB of DRAM and several I\/O subsystems that can be used to enable faster, larger and higher fidelity computer architecture or other systems research. Objective: Revitalizing Computer Architecture Research The Problem Computer Architecture is increasingly incremental, and boring. Many papers […]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","footnotes":""},"research-area":[13552,13547],"msr-locale":[268875],"msr-impact-theme":[],"msr-pillar":[],"class_list":["post-169466","msr-project","type-msr-project","status-publish","hentry","msr-research-area-hardware-devices","msr-research-area-systems-and-networking","msr-locale-en_us","msr-archive-status-active"],"msr_project_start":"2008-02-26","related-publications":[145451,153745,157368,159453,160486],"related-downloads":[],"related-videos":[],"related-groups":[],"related-events":[],"related-opportunities":[],"related-posts":[],"related-articles":[],"tab-content":[],"slides":[],"related-researchers":[{"type":"user_nicename","value":"cthacker","display_name":"Chuck Thacker","author_link":"Chuck Thacker<\/a>","is_active":false,"user_id":31483,"last_first":"Thacker, Chuck","people_section":0,"alias":"cthacker"}],"msr_research_lab":[],"msr_impact_theme":[],"_links":{"self":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project"}],"about":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/types\/msr-project"}],"version-history":[{"count":1,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466\/revisions"}],"predecessor-version":[{"id":215845,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466\/revisions\/215845"}],"wp:attachment":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/media?parent=169466"}],"wp:term":[{"taxonomy":"msr-research-area","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/research-area?post=169466"},{"taxonomy":"msr-locale","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-locale?post=169466"},{"taxonomy":"msr-impact-theme","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-impact-theme?post=169466"},{"taxonomy":"msr-pillar","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-pillar?post=169466"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
The Solution: BEE3<\/h2>\n
BEE3 stands for the Berkeley Emulation Engine version 3. The BEE3 system is a 2U chassis with a tightly-couple 4 FPGA system that is a vehicle for Computer Architecture Research. In particular, the BEE3 is the target platform for the Research Accelerator for Multiple Processors (RAMP (opens in new tab)<\/span><\/a>). RAMP is a collection of six universities (Berkeley, Stanford, UW, UT, CMU, and MIT) and several industry partners including: Microsoft Research, Xilinx, Sun Microsystems and IBM. The BEE3 is a scalable platform, 1 to 64 2U systems, that facilitates research in a multiple areas: Computer Architecture, Systems, OS and Software, Memory Hierarchy and Storage, and various Application\/Algorithm Accelerators, to name a few.<\/p>\n\t The BEE3 design has been licensed to BEEcube<\/b> (opens in new tab)<\/span><\/a>. (opens in new tab)<\/span><\/a> Please contact BEEcube for product ordering and pricing information.<\/p>\n The BEE3 DDR2 controller is available at the Microsoft Research downloads repository. You can also search for the controller by name: “DDR2 DRAM Controller for BEE3”.<\/p>\n The pictures below show the rack mounted 2U BEE3 system and the inside of the 2U system with the major components labeled.<\/p>\n The BEE3 system is made up of a Main<\/b> Printed Circuit Board (PCB) and a Control & I\/O<\/b> PCB with the following components:<\/p>\n The BEE3 Main PCB connectivity is shown in the diagram below:<\/p>\n The BEE3 (Berkeley Emulation Engine, version 3) is a multi-FPGA system with up to 64 GB of DRAM and several I\/O subsystems that can be used to enable faster, larger and higher fidelity computer architecture or other systems research. Objective: Revitalizing Computer Architecture Research The Problem Computer Architecture is increasingly incremental, and boring. Many papers […]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","footnotes":""},"research-area":[13552,13547],"msr-locale":[268875],"msr-impact-theme":[],"msr-pillar":[],"class_list":["post-169466","msr-project","type-msr-project","status-publish","hentry","msr-research-area-hardware-devices","msr-research-area-systems-and-networking","msr-locale-en_us","msr-archive-status-active"],"msr_project_start":"2008-02-26","related-publications":[145451,153745,157368,159453,160486],"related-downloads":[],"related-videos":[],"related-groups":[],"related-events":[],"related-opportunities":[],"related-posts":[],"related-articles":[],"tab-content":[],"slides":[],"related-researchers":[{"type":"user_nicename","value":"cthacker","display_name":"Chuck Thacker","author_link":"Chuck Thacker<\/a>","is_active":false,"user_id":31483,"last_first":"Thacker, Chuck","people_section":0,"alias":"cthacker"}],"msr_research_lab":[],"msr_impact_theme":[],"_links":{"self":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project"}],"about":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/types\/msr-project"}],"version-history":[{"count":1,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466\/revisions"}],"predecessor-version":[{"id":215845,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-project\/169466\/revisions\/215845"}],"wp:attachment":[{"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/media?parent=169466"}],"wp:term":[{"taxonomy":"msr-research-area","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/research-area?post=169466"},{"taxonomy":"msr-locale","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-locale?post=169466"},{"taxonomy":"msr-impact-theme","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-impact-theme?post=169466"},{"taxonomy":"msr-pillar","embeddable":true,"href":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/wp\/v2\/msr-pillar?post=169466"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}\n\t\t\t\t\t\t\t\t
<\/span><\/span><\/span><\/span><\/p>\n\n
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<\/span><\/span><\/p>\n\t\t\t<\/div>\n\t\t<\/div>\n\t<\/li>\n\t\t\n