{"id":1169056,"date":"2026-04-20T09:50:20","date_gmt":"2026-04-20T16:50:20","guid":{"rendered":"https:\/\/www.microsoft.com\/en-us\/research\/publication\/tilelang-bridge-programmability-and-performance-in-modern-neural-kernels\/"},"modified":"2026-05-08T09:17:50","modified_gmt":"2026-05-08T16:17:50","slug":"tilelang-bridge-programmability-and-performance-in-modern-neural-kernels","status":"publish","type":"msr-research-item","link":"https:\/\/www.microsoft.com\/en-us\/research\/publication\/tilelang-bridge-programmability-and-performance-in-modern-neural-kernels\/","title":{"rendered":"TileLang: A Composable Tiled Programming Model for AI Systems"},"content":{"rendered":"<p>Modern AI workloads rely heavily on optimized computing kernels for both training and inference. These AI kernels follow well-defined data-flow patterns, such as moving tiles between DRAM and SRAM and performing a sequence of computations on those tiles. However, writing high-performance kernels remains complex despite the clarity of these patterns. Achieving peak performance requires careful, hardware-centric optimizations to fully leverage modern accelerators. While domain-specific compilers attempt to reduce the burden of writing high-performance kernels, they often struggle with usability and expressiveness gaps. In this paper, we present TileLang, a generalized tiled programming model for more efficient AI Kernel programming. TileLang decouples scheduling space (thread binding, layout, tensorize and pipeline) from dataflow, and encapsulated them as a set of customization annotations and primitives. This approach allows users to focus on the kernel&#8217;s data-flow itself, while leaving most other optimizations to compilers. We conduct comprehensive experiments on commonly-used devices, across numerous experiments, our evaluation shows that TileLang can achieve state-of-the-art performance in key kernels, demonstrating that its unified block-and-thread paradigm and transparent scheduling capabilities deliver both the power and flexibility demanded by modern AI system development.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Modern AI workloads rely heavily on optimized computing kernels for both training and inference. These AI kernels follow well-defined data-flow patterns, such as moving tiles between DRAM and SRAM and performing a sequence of computations on those tiles. However, writing high-performance kernels remains complex despite the clarity of these patterns. Achieving peak performance requires careful, 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