{"id":162882,"date":"2013-02-01T00:00:00","date_gmt":"2013-02-01T08:00:00","guid":{"rendered":"https:\/\/www.microsoft.com\/en-us\/research\/msr-research-item\/efficiently-solving-quantified-bit-vector-formulas-2\/"},"modified":"2018-10-16T20:00:22","modified_gmt":"2018-10-17T03:00:22","slug":"efficiently-solving-quantified-bit-vector-formulas-2","status":"publish","type":"msr-research-item","link":"https:\/\/www.microsoft.com\/en-us\/research\/publication\/efficiently-solving-quantified-bit-vector-formulas-2\/","title":{"rendered":"Efficiently Solving Quantified Bit-Vector Formulas"},"content":{"rendered":"<p>In recent years, bit-precise reasoning has gained importance in hardware and software veri\ufb01cation. Of renewed interest is the use of symbolic reasoning for synthesising loop invariants, ranking functions, or whole program fragments and hardware circuits. Solvers for the quanti\ufb01er-free fragment of bit-vector logic exist and often rely on SAT solvers for e\ufb03ciency. However, many techniques require quanti\ufb01ers in bit-vector formulas to avoid an exponential blow-up during construction. Solvers for quanti\ufb01ed formulas usually \ufb02atten the input to obtain a quanti\ufb01ed Boolean formula, losing much of the word-level information in the formula. We present a new approach based on a set of e\ufb00ective word-level simpli\ufb01cations that are traditionally employed in automated theorem proving, heuristic quanti\ufb01er instantiation methods used in SMT solvers, and model \ufb01nding techniques based on skeletons\/templates. Experimental results on two di\ufb00erent types of benchmarks indicate that our method outperforms the traditional \ufb02attening approach by multiple orders of magnitude of runtime.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>In recent years, bit-precise reasoning has gained importance in hardware and software veri\ufb01cation. Of renewed interest is the use of symbolic reasoning for synthesising loop invariants, ranking functions, or whole program fragments and hardware circuits. Solvers for the quanti\ufb01er-free fragment of bit-vector logic exist and often rely on SAT solvers for e\ufb03ciency. However, many techniques [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","msr-author-ordering":[{"type":"user_nicename","value":"cwinter","user_id":"31491"},{"type":"user_nicename","value":"youssefh","user_id":"35047"},{"type":"user_nicename","value":"leonardo","user_id":"32646"}],"msr_publishername":"Springer","msr_publisher_other":"","msr_booktitle":"","msr_chapter":"","msr_edition":"Formal Methods in System Design","msr_editors":"","msr_how_published":"","msr_isbn":"","msr_issue":"","msr_journal":"Formal Methods in System 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