A sensitive floating-gate integrator technique using single-poly pFET NVM technology has been developed and utilized to enable technology transfer and improved fab matching of logic NVM designs in a standard logic CMOS process. With utilization of our technique, an abnormal parasitic RC relaxation phenomenon observed in a floating gate design was effectively characterized across six foundries and from 0.35\u00b5m to 90nm logic CMOS technologies. The technique is used as a powerful tool to debug manufacturing issues and to monitor the manufacturability of advanced technologies.<\/p>\n","protected":false},"excerpt":{"rendered":"
A sensitive floating-gate integrator technique using single-poly pFET NVM technology has been developed and utilized to enable technology transfer and improved fab matching of logic NVM designs in a standard logic CMOS process. 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