An N-LDMOS (N-channel laterally diffused drain MOSFET), fabricated in a standard CMOS process, is used to provide relatively high-voltage (HV\/spl sim\/12 V) capability without any extra process steps. However, there is very little information available for LDMOS devices with technologies below 0.35 \/spl mu\/m using STI isolation. In this work, we investigated the typical layout geometry dependence of device drain current leakage, drain breakdown and on-state current characteristics, with devices fabricated in a standard logic 0.18 \/spl mu\/m and 0.25 \/spl mu\/m process. Furthermore, for the first time, a dependence on layout orientation and its effect on hot-carrier injection (HCI) reliability are reported.<\/p>\n","protected":false},"excerpt":{"rendered":"
An N-LDMOS (N-channel laterally diffused drain MOSFET), fabricated in a standard CMOS process, is used to provide relatively high-voltage (HV\/spl sim\/12 V) capability without any extra process steps. However, there is very little information available for LDMOS devices with technologies below 0.35 \/spl mu\/m using STI isolation. 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