{"id":415760,"date":"2017-07-23T00:00:17","date_gmt":"2017-07-23T07:00:17","guid":{"rendered":"https:\/\/www.microsoft.com\/en-us\/research\/?p=415760"},"modified":"2017-07-25T11:44:46","modified_gmt":"2017-07-25T18:44:46","slug":"second-version-hololens-hpu-will-incorporate-ai-coprocessor-implementing-dnns","status":"publish","type":"post","link":"https:\/\/www.microsoft.com\/en-us\/research\/blog\/second-version-hololens-hpu-will-incorporate-ai-coprocessor-implementing-dnns\/","title":{"rendered":"Second version of HoloLens HPU will incorporate AI coprocessor for implementing DNNs"},"content":{"rendered":"

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By Marc Pollefeys<\/a>, Director of Science, HoloLens<\/em><\/p>\n

It is not an exaggeration to say that deep learning has taken the world of computer vision, and many other recognition tasks, by storm. Many of the most difficult recognition problems have seen gains over the past few years that are astonishing.<\/p>\n

Although we have seen large improvements in the accuracy of recognition as a result of Deep Neural Networks (DNNs), deep learning approaches have two well-known challenges: they require large amounts of labelled data for training, and they require a type of compute that is not amenable to current general purpose processor\/memory architectures. Some companies have responded with architectures designed to address the particular type of massively parallel compute required for DNNs, including our own use of FPGAs (opens in new tab)<\/span><\/a>, for example, but to date these approaches have primarily enhanced existing cloud computing fabrics.<\/p>\n

But I work on HoloLens<\/a>, and in HoloLens, we’re in the business of making untethered mixed reality devices. We put the battery on your head, in addition to the compute, the sensors, and the display. Any compute we want to run locally for low-latency, which you need for things like hand-tracking, has to run off the same battery that powers everything else. So what do you do?<\/p>\n

You create custom silicon to do it.<\/p>\n