Ron Paulsen

Principal Program Manager

论文与出版物

查看方式：

- A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting
  
  Becky Mieloszyk, Hope Twede, Jonathan Lester, Jeremiah (Miah) Wander, Sumit Basu, Gabe Cohn, Greg Smith, Sidhant Gupta, Desney Tan, Nicolas Villar, Moni Wolf, Sailaja Malladi, Ron Paulsen, Scott Saponas
  
  IEEE Journal of Biomedical and Health Informatics | July 2022, 第 26 卷(7): pp. 2864-2875
  
  Publication
- Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | November 2008, 第 55 卷(12): pp. 3476-3481
  
  DOI Publication Publication
- Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond
  
  Ron Paulsen
  
  2007 International Integrated Reliability Workshop | September 2007
  
  DOI Publication Publication
- Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | August 2007, 第 54 卷(9): pp. 2526-2530
  
  DOI Publication Publication Publication Publication
- Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device
  
  Ron Paulsen
  
  2007 International Reliability Physics Symposium | March 2007
  
  DOI Publication Publication
- A Sensitive Technique to Enable Technology Transfer and Fab Matching in Deep Sub-Micron Technologies ISSM Paper: PC-O-193
  
  Ron Paulsen
  
  December 2006
  
  PDF
- Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications
  
  Ron Paulsen
  
  May 2006
  
  DOI Publication
- Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory
  
  Ron Paulsen
  
  2005 International Integrated Reliability Workshop | October 2005
  
  DOI Publication
- Measurement of ultralow gate tunneling currents using floating-gate integrator technique
  
  Ron Paulsen
  
  IEEE Electron Device Letters | May 2005, 第 26 卷(5): pp. 329-331
  
  DOI Publication Publication
- Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process
  
  Ron Paulsen
  
  2005 International Reliability Physics Symposium | April 2005
  
  DOI Publication
- Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes
  
  Ron Paulsen
  
  IEEE Transactions on Device and Materials Reliability | December 2004, 第 4 卷(3): pp. 353-358
  
  DOI Publication
- A reliability methodology for low temperature data retention in floating gate non-volatile memories
  
  Ron Paulsen
  
  2001 International Reliability Physics Symposium | April 2001
  
  DOI Publication
- Post poly-Si gate rapid thermal nitridation for boron penetration reduction and oxide reliability improvement
  
  Ron Paulsen
  
  IEEE Electron Device Letters | June 1998, 第 19 卷(7): pp. 237-240
  
  DOI Publication
- Process integration of an interlevel dielectric (ILDO) module using a building-in reliability approach
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | February 1998, 第 45 卷(3): pp. 655-664
  
  DOI Publication Publication
- Observation and characterization of near-interface oxide traps with C-V techniques
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | October 1995, 第 42 卷(11): pp. 2004-2009
  
  DOI Publication Publication Publication
- MOS device reliability studies under LabVIEW environment
  
  Ron Paulsen
  
  1994 International Electron Devices Meeting | December 1994
  
  DOI Publication
- Theory and application of charge pumping for the characterization of Si-SiO/sub 2/ interface and near-interface oxide traps
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | June 1994, 第 41 卷(7): pp. 1213-1216
  
  DOI Publication Publication
- Observation of near-interface oxide traps with the charge-pumping technique
  
  Ron Paulsen
  
  IEEE Electron Device Letters | November 1992, 第 13 卷(12): pp. 627-629
  
  DOI Publication Publication

- A reliability methodology for low temperature data retention in floating gate non-volatile memories
  
  Ron Paulsen
  
  2001 International Reliability Physics Symposium | April 2001
  
  DOI Publication
- Post poly-Si gate rapid thermal nitridation for boron penetration reduction and oxide reliability improvement
  
  Ron Paulsen
  
  IEEE Electron Device Letters | June 1998, 第 19 卷(7): pp. 237-240
  
  DOI Publication
- Process integration of an interlevel dielectric (ILDO) module using a building-in reliability approach
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | February 1998, 第 45 卷(3): pp. 655-664
  
  DOI Publication Publication
- Observation and characterization of near-interface oxide traps with C-V techniques
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | October 1995, 第 42 卷(11): pp. 2004-2009
  
  DOI Publication Publication Publication
- MOS device reliability studies under LabVIEW environment
  
  Ron Paulsen
  
  1994 International Electron Devices Meeting | December 1994
  
  DOI Publication
- Theory and application of charge pumping for the characterization of Si-SiO/sub 2/ interface and near-interface oxide traps
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | June 1994, 第 41 卷(7): pp. 1213-1216
  
  DOI Publication Publication
- Observation of near-interface oxide traps with the charge-pumping technique
  
  Ron Paulsen
  
  IEEE Electron Device Letters | November 1992, 第 13 卷(12): pp. 627-629
  
  DOI Publication Publication
- A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting
  
  Becky Mieloszyk, Hope Twede, Jonathan Lester, Jeremiah (Miah) Wander, Sumit Basu, Gabe Cohn, Greg Smith, Sidhant Gupta, Desney Tan, Nicolas Villar, Moni Wolf, Sailaja Malladi, Ron Paulsen, Scott Saponas
  
  IEEE Journal of Biomedical and Health Informatics | July 2022, 第 26 卷(7): pp. 2864-2875
  
  Publication
- Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | November 2008, 第 55 卷(12): pp. 3476-3481
  
  DOI Publication Publication
- Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond
  
  Ron Paulsen
  
  2007 International Integrated Reliability Workshop | September 2007
  
  DOI Publication Publication
- Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | August 2007, 第 54 卷(9): pp. 2526-2530
  
  DOI Publication Publication Publication Publication
- Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device
  
  Ron Paulsen
  
  2007 International Reliability Physics Symposium | March 2007
  
  DOI Publication Publication
- A Sensitive Technique to Enable Technology Transfer and Fab Matching in Deep Sub-Micron Technologies ISSM Paper: PC-O-193
  
  Ron Paulsen
  
  December 2006
  
  PDF
- Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications
  
  Ron Paulsen
  
  May 2006
  
  DOI Publication
- Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory
  
  Ron Paulsen
  
  2005 International Integrated Reliability Workshop | October 2005
  
  DOI Publication
- Measurement of ultralow gate tunneling currents using floating-gate integrator technique
  
  Ron Paulsen
  
  IEEE Electron Device Letters | May 2005, 第 26 卷(5): pp. 329-331
  
  DOI Publication Publication
- Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process
  
  Ron Paulsen
  
  2005 International Reliability Physics Symposium | April 2005
  
  DOI Publication
- Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes
  
  Ron Paulsen
  
  IEEE Transactions on Device and Materials Reliability | December 2004, 第 4 卷(3): pp. 353-358
  
  DOI Publication
- A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting
  
  Becky Mieloszyk, Hope Twede, Jonathan Lester, Jeremiah (Miah) Wander, Sumit Basu, Gabe Cohn, Greg Smith, Sidhant Gupta, Desney Tan, Nicolas Villar, Moni Wolf, Sailaja Malladi, Ron Paulsen, Scott Saponas
  
  IEEE Journal of Biomedical and Health Informatics | July 2022, 第 26 卷(7): pp. 2864-2875
  
  Publication

- A reliability methodology for low temperature data retention in floating gate non-volatile memories
  
  Ron Paulsen
  
  2001 International Reliability Physics Symposium | April 2001
  
  DOI Publication
- MOS device reliability studies under LabVIEW environment
  
  Ron Paulsen
  
  1994 International Electron Devices Meeting | December 1994
  
  DOI Publication
- Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond
  
  Ron Paulsen
  
  2007 International Integrated Reliability Workshop | September 2007
  
  DOI Publication Publication
- Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device
  
  Ron Paulsen
  
  2007 International Reliability Physics Symposium | March 2007
  
  DOI Publication Publication
- Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications
  
  Ron Paulsen
  
  May 2006
  
  DOI Publication
- Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory
  
  Ron Paulsen
  
  2005 International Integrated Reliability Workshop | October 2005
  
  DOI Publication
- Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process
  
  Ron Paulsen
  
  2005 International Reliability Physics Symposium | April 2005
  
  DOI Publication
- Post poly-Si gate rapid thermal nitridation for boron penetration reduction and oxide reliability improvement
  
  Ron Paulsen
  
  IEEE Electron Device Letters | June 1998, 第 19 卷(7): pp. 237-240
  
  DOI Publication
- Process integration of an interlevel dielectric (ILDO) module using a building-in reliability approach
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | February 1998, 第 45 卷(3): pp. 655-664
  
  DOI Publication Publication
- Observation and characterization of near-interface oxide traps with C-V techniques
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | October 1995, 第 42 卷(11): pp. 2004-2009
  
  DOI Publication Publication Publication
- Theory and application of charge pumping for the characterization of Si-SiO/sub 2/ interface and near-interface oxide traps
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | June 1994, 第 41 卷(7): pp. 1213-1216
  
  DOI Publication Publication
- Observation of near-interface oxide traps with the charge-pumping technique
  
  Ron Paulsen
  
  IEEE Electron Device Letters | November 1992, 第 13 卷(12): pp. 627-629
  
  DOI Publication Publication
- A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting
  
  Becky Mieloszyk, Hope Twede, Jonathan Lester, Jeremiah (Miah) Wander, Sumit Basu, Gabe Cohn, Greg Smith, Sidhant Gupta, Desney Tan, Nicolas Villar, Moni Wolf, Sailaja Malladi, Ron Paulsen, Scott Saponas
  
  IEEE Journal of Biomedical and Health Informatics | July 2022, 第 26 卷(7): pp. 2864-2875
  
  Publication
- Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | November 2008, 第 55 卷(12): pp. 3476-3481
  
  DOI Publication Publication
- Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices
  
  Ron Paulsen
  
  IEEE Transactions on Electron Devices | August 2007, 第 54 卷(9): pp. 2526-2530
  
  DOI Publication Publication Publication Publication
- Measurement of ultralow gate tunneling currents using floating-gate integrator technique
  
  Ron Paulsen
  
  IEEE Electron Device Letters | May 2005, 第 26 卷(5): pp. 329-331
  
  DOI Publication Publication
- Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes
  
  Ron Paulsen
  
  IEEE Transactions on Device and Materials Reliability | December 2004, 第 4 卷(3): pp. 353-358
  
  DOI Publication
- A Sensitive Technique to Enable Technology Transfer and Fab Matching in Deep Sub-Micron Technologies ISSM Paper: PC-O-193
  
  Ron Paulsen
  
  December 2006
  
  PDF

Ron Paulsen

论文与出版物

A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting

Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide

Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond

Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices

Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device

A Sensitive Technique to Enable Technology Transfer and Fab Matching in Deep Sub-Micron Technologies ISSM Paper: PC-O-193

Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications

Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

A reliability methodology for low temperature data retention in floating gate non-volatile memories

Post poly-Si gate rapid thermal nitridation for boron penetration reduction and oxide reliability improvement

Process integration of an interlevel dielectric (ILDO) module using a building-in reliability approach

Observation and characterization of near-interface oxide traps with C-V techniques

MOS device reliability studies under LabVIEW environment

Theory and application of charge pumping for the characterization of Si-SiO/sub 2/ interface and near-interface oxide traps

Observation of near-interface oxide traps with the charge-pumping technique

A reliability methodology for low temperature data retention in floating gate non-volatile memories

Post poly-Si gate rapid thermal nitridation for boron penetration reduction and oxide reliability improvement

Process integration of an interlevel dielectric (ILDO) module using a building-in reliability approach

Observation and characterization of near-interface oxide traps with C-V techniques

MOS device reliability studies under LabVIEW environment

Theory and application of charge pumping for the characterization of Si-SiO/sub 2/ interface and near-interface oxide traps

Observation of near-interface oxide traps with the charge-pumping technique

A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting

Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide

Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond

Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices

Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device

A Sensitive Technique to Enable Technology Transfer and Fab Matching in Deep Sub-Micron Technologies ISSM Paper: PC-O-193

Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications

Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting

A reliability methodology for low temperature data retention in floating gate non-volatile memories

MOS device reliability studies under LabVIEW environment

Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond

Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device

Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications

Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory

Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process

Post poly-Si gate rapid thermal nitridation for boron penetration reduction and oxide reliability improvement

Process integration of an interlevel dielectric (ILDO) module using a building-in reliability approach

Observation and characterization of near-interface oxide traps with C-V techniques

Theory and application of charge pumping for the characterization of Si-SiO/sub 2/ interface and near-interface oxide traps

Observation of near-interface oxide traps with the charge-pumping technique

A Comparison of Wearable Tonometry, Photoplethysmography, and Electrocardiography for Cuffless Measurement of Blood Pressure in an Ambulatory Setting

Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide

Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

A Sensitive Technique to Enable Technology Transfer and Fab Matching in Deep Sub-Micron Technologies ISSM Paper: PC-O-193