Fault-tolerant Computing using a Hybrid Nano-CMOS Architecture

Architectures based on nanoscale molecular devices are attracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nanotechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they do suffer from very defect-prone manufacturing processes. This is further exacerbated by testing complexities where it is nearly impossible to detect and localize all faults in a large nanoscale chip. As a result, fault tolerance is necessary to make nanoscale architectures practical and realistic. Although reconfiguration can be used to compile around known defects on a chip, a large fraction of defects may remain hidden if they cannot be discovered by testing. Furthermore, the small structures in nanoscale architectures are particularly susceptible to transient faults which can produce arbitrary soft errors. For the first time, we propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our architecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. A companion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.