Parade: A versatile parallel architecture for accelerating pulse train clustering

In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulse-trains. This is a commonly performed task in various areas of signal processing applications, such as satellite communication. Most of these applications require the identification of the main characteristics of pulse-trains such as frequency. Previously suggested techniques for solving the clustering problem are restricted with several limiting assumptions. In contrast, Parade, based off a parallelized and improved version of the sequential search algorithm, solves the deinterleaving problem significantly faster and in a more general case by considering all conditions such as jitter, dropped pulses, arbitrary start and end points. Our scheme employs several parameters, such as the number of deinterleaving modules and the number of memory elements, in order to achieve a desirable combination of accuracy, speed, memory usage and area. Using an 8-way parallel architecture, Parade improves the PRI accuracy by 27% compared to the nonparallel baseline architecture. Our design, when synthesized on 90nm technology node, performs 940x faster compared to a software-based histogram technique.