Static and dynamic power constraints are steering chip manufacturers to build single-ISA Asymmetric Multicore Processors (AMPs) with big and small cores. To deliver on their energy efficiency potential, schedulers must consider core sensitivity, load balance, and the critical path.
We improved the current managed runtime scheduler for asymmetric multicore
processors. Based on the criticality, performance sensitivity, and priority information
of each thread along with workload balancing information, the scheduler will assign
threads to appropriate core types. Compared to OS management, performance is
improved up to 31%, and energy is reduced by 15%.