The MIPS-to-Verilog (M2V) compiler translates blocks of MIPS machine code into a hardware design represented in Verilog. M2V is part of a tool-chain that automatically accelerates software applications on hardware platforms such as the eMIPS processor, a dynamically extensible processor realized on the Virtex-4 XC4LX25 FPGA. The M2V compiler can accelerate blocks that include load and stores, supports interrupts and TLB misses, and automatically encodes extended instructions for minimal latency. The new version supports the composition of multiple basic blocks using four basic control patterns. The optimization techniques make use of path-based scheduling algorithms derived from dataflow static scheduling, and from control-flow state machines. Simulation results indicate a factor of 22 in performance improvement in the case of a simple self-looped basic block.