Embedded Memory in Nanometer Regime: Improving Yield, Scalability, and Error Resiliency with Low-overhead Multi-bit Error Coding

In modern microprocessors and systems-on-a-chip, the embedded memory system plays a key role in determining the design’s overall performance, power, area, reliability, and yield. As fabrication process technologies scale into the deep nanometer regime, increasing device variability poses particular difficulties for memory design due to the large number of variation-sensitive near minimum-sized devices in the cell arrays which often must achieve working circuits out beyond six sigma of variation to meet design targets at economically acceptable yields. Furthermore, as scaling progresses, soft errors in the memory system will also increase in frequency and scope, and single error events are more likely to cause large-scale multi-bit errors. Researchers have developed a number of variation- and soft error-tolerant techniques to mitigate parametric yield loss, performance loss, and information loss, but these techniques incur extremely high VLSI overheads.
In this talk, I will propose using multi-bit error correcting codes (ECC) to provide in-line data correction to combat variation-induced memory cell failures as well as maintain soft-error resilience. I will also explore how this increased resilience can be traded-off for higher-density bitcells, higher performance, greater cell stability, or lower power design, while maintaining high yield. Finally, I will present an efficient multi-bit ECC technique tailored for correcting manufacture-time variation errors along with soft-errors by making use of two-dimensional (2D) erasure coding. The proposed scheme when combined with a small amount of row redundancy can improve the SRAM access latency, power, and stability by over 40% on average, while maintaining near 100% yield and run-time reliability. Conventional schemes require >70% variability-hardened redundancy or must disable >70% of memory to achieve the same level of tolerance.