Software- Assisted Hardware Reliability

June 30, 2010
Vijay Janapa Reddi | AMD Research Labs

In the era of nanoscale technology scaling, we are facing the limits of physics, challenging robust and reliable microprocessor design and fabrication. As these trends continue, guaranteeing correctness of execution using traditional circuit-level solutions is becoming prohibitively expensive and impractical. This talk demonstrates the benefits of abstracting circuit-level challenges to the higher layers of execution, specifically the run-time architecture and software stack. Reliability challenges are broadly classified into process, voltage, and thermal (PVT) variations. Discussing and evaluating hardware-software co-design to mitigate voltage variation, I demonstrate that such an approach is not only sustainable in the long run, but also cost-effective, specifically in the commodity microprocessor market segment.

Speaker Details

Vijay Janapa Reddi is a recent PhD graduate from the computer science department at Harvard University, soon to be joining AMD research labs in Austin. His research interests are in the area of computer systems. He is specifically interested in understanding current and future application and processor design trends to help develop robust computing platforms in light of reliability challenges. He is interested in applying his background in virtual machines, binary translation and processor architecture to successfully mitigate circuit-level reliability challenges via hardware-software co-design. He has an MS in computer engineering from the University of Colorado at Boulder, and he is well known for his contributions to the community via Pin, a binary instrumentation tool that is widely in use both by academia and industry for program introspection, which he co-developed while he was at Intel.