Simulate & Eliminate – A Design Methodology for Application Specific, Multi-Core Architectures

April 22, 2010
Ryan Kastner | University of California, San Diego

Processor specialization is a prevalent trend in computing. This started with digital signal processors and has since moved to application domains including networking, wireless communication, audio and vision. These processors are typically developed for embedded computing systems, which have stringent constraints on performance. Achieving the desired requirements demands careful tuning of the underlying architecture.

This talk describes our tool, Simulate & Eliminate (S&E), which produces synthesizable HDL for application specific, multi-core architectures. S&E employs a novel top-to-bottom design methodology to generate correct-by-construction and cycle-accurate multi-core architectures for a given application. The top-to-bottom design methodology provides simplicity (through the use of a simple tool chain and programming model), flexibility (through the capability of using different specification languages as well as different parameterization options), scalability (through the ability to handle complex applications) and power/energy efficiency (through the use of clock and power gating and power and frequency scaling).

S&E starts from a fully connected, general purpose, multi-core architecture and pares away unneeded functionality to create an application specific, multi-core architecture. This not only removes unneeded functional units, but also unnecessary interconnect, control logic and memory. We show that there are substantial opportunities to eliminate unneeded functionality and create an application specific architecture for executing a specific (set of) application(s). We focus the design of our tool on digital signal processing applications, such as real-time vision, acoustic and radio frequency communication; however, our tool is broadly applicable to any application.

Speaker Details

Ryan Kastner is an associate professor in the Department of Computer Science and Engineering at the University of California, San Diego. He received a PhD in Computer Science (2002) at UCLA, a masters degree in engineering (2000) and bachelor degrees (BS) in both Electrical Engineering and Computer Engineering (1999), all from Northwestern University. He spent the first five years after his PhD as a professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. Professor Kastner’s current research interests reside in the realm of embedded system design, in particular, the use of reconfigurable computing devices for digital signal processing as well as hardware security. He has published over 100 technical articles, and has authored three books, “Synthesis Techniques and Optimizations for Reconfigurable Systems”, “Arithmetic Optimizations for Polynomial Expressions and Linear Systems” and “Handbook on FPGA Design Security”. He has served as member of numerous conference technical committees spanning topics like reconfigurable computing (ISFPGA, FPL, FPT, ERSA, RAW, ARC), electronic design automation (DAC, ICCAD, DATE, ICCD, GLSVLSI), wireless communication (GLOBECOM, SUTC), hardware security (HOST) and underwater networking (WUWNet). He serves on the editorial board for the IEEE Embedded Systems Letters.