Our investment in two leading Swiss education and research institutions ETH and EPFL will continue through 2021.
The Swiss Joint Research Center (Swiss JRC) is a collaborative research engagement between Microsoft Research and the two universities that make up the Swiss Federal Institutes of Technology: ETH Zurich (Eidgenössische Technische Hochschule Zürich, which serves German-speaking students) and EPFL (École Polytechnique Fédérale de Lausanne, which serves French-speaking students). The Swiss JRC is a continuation of a collaborative engagement that was initiated by Steve Ballmer in 2008, when the same three partners embarked on ICES (Microsoft Innovation Cluster for Embedded Software).
Over the years, the Swiss JRC supported projects in cutting-edge research areas including Artificial Intelligence (AI), Mixed Reality (MR), customized hardware for data centers, systems, and security. In its first phase (2014-2016) 7 projects were supported (4 at ETH and 3 at EPFL). In the second phase 10 (4 at ETH and 6 at EPFL). In the beginning of each phase, the Swiss JRC announces an open and competitive Call for Proposals to which ETH and EPFL faculty can apply with “collaborative” research proposals. “Collaborative” means that research proposals must name a Microsoft co-author who contributes to the proposal substantially. A third Call for Proposals was announced in the summer of 2018 and a new round of projects will start in early 2019.
The Swiss JRC is governed by a Steering Committee consisting of representatives from ETH Zurich, EPFL, Microsoft Switzerland, and Microsoft Research that ensures the smooth operation of the engagement for all three partners and decides on strategic direction. The Steering Committee reviews, ranks, and selects projects based on the potential scientific advance, impact, and alignment with Microsoft research priorities and invites to annual workshops where research teams come together to provide progress updates and exchange ideas.
Swiss JRC Steering Committee 2018
Overviews for projects dating from 2017-2018
Toward Resource-Efficient Datacenters
Florin Dinu, EPFL
Christos Gkantsidis, Microsoft Research
Sergey Legtchenko, Microsoft Research
The goal of our project is to improve the utilization of server resources in datacenters. Our proposed approach was to attain a better understanding of the resource requirements of data-parallel applications, and then incorporate this understanding into the design of more informed and efficient datacenter (cluster) schedulers. While pursuing these directions, we have identified two related challenges that we believe hold the key towards significant additional improvements in application performance, as well as cluster-wide resource utilization. We will explore these two challenges as a continuation of our project. These two challenges are: resource inter-dependency and time-varying resource requirements. Resource inter-dependency refers to the impact that a change in the allocation of one server resource (memory, CPU, network bandwidth, disk bandwidth) to an application has on that application’s need for the other resources. Time-varying resource requirements refers to the fact that over the lifetime of an application, its resource requirements may vary. Studying these two challenges together holds the potential for improving resource utilization by aggressively, but safely, collocating applications on servers.
Near-Memory System Services
Babak Falsafi, EPFL
Stavros Volos, Microsoft Research
Near-memory processing (NMP) is a promising approach to satisfy the performance requirements of modern datacenter services at a fraction of modern infrastructure’s power. NMP leverages emerging die-stacked DRAM technology, which (a) delivers high-bandwidth memory access, and (b) features a logic die that provides the opportunity for dramatic data movement reduction – and consequently energy savings – by pushing computation closer to the data. In the precursor to this project (the Microsoft Research European PhD Scholarship), we evaluated algorithms suitable for database join operators near memory. We showed that while sort join has been conventionally thought of as inferior to hash join in CPU performance, near-memory processing favors sequential over random memory access, making sort join superior in performance and efficiency as a near-memory service.
In this project, we propose to answer the following questions:
- What data-specific functionality should be implemented near memory (for example, data filtering, data reorganization, data fetch)?
- What ubiquitous, yet simple system-level functionality should be implemented near memory (for example, security, compression, remote memory access)?
- How should the services be integrated with the system (for example, how does the software use them)?
- How do we employ near-threshold logic in near-memory processing?
Coltrain: Co-located Deep Learning Training and Inference
Babak Falsafi, EPFL
Martin Jaggi, EPFL
Eric Chung, Microsoft Research
Deep Neural Networks (DNNs) have emerged as the algorithms of choice for many prominent machine learning tasks, including image analysis and speech recognition. In datacenters, DNNs are trained on massive datasets in order to improve prediction accuracy. While the computational demands for performing online inference in an already trained DNN can be furnished by commodity servers, training DNNs often requires computational density that is orders of magnitude higher than that provided by modern servers. As such, operators often use dedicated clusters of GPUs for training DNNs. Unfortunately, dedicated GPU clusters introduce significant additional acquisition costs, break the continuity and homogeneity of datacenters, and are inherently not scalable.
FPGAs are appearing in server nodes either as daughter cards (for example, Catapult) or coherent sockets (for example, Intel HARP), providing a great opportunity to co-locate inference and training on the same platform. While these designs enable natural continuity for platforms, co-locating inference and training on a single node faces a number of key challenges. First, FPGAs inherently suffer from low computational density. Second, conventional training algorithms do not scale due to inherent high communication requirements. Finally, co-location may lead to contention requiring mechanisms to prioritize inference over training.
In this project, we will address these fundamental challenges in DNN inference/training co-location on servers with integrated FPGAs. Our goals are to:
- Redesign training and inference algorithms to take advantage of DNN’s inherent tolerance for low-precision operations.
- Identify good candidates for hard-logic blocks for the next generations of FPGAs.
- Redesign DNN training algorithms to aggressively approximate and compress intermediate results, to target communication bottlenecks and scale the training of single networks to an arbitrary number of nodes.
- Implement FPGA-based load-balancing techniques to provide latency guarantees for inference tasks under heavy loads and enable the use of idle accelerator cycles to train networks when operating under lower loads.
From Companion Drones to Personal Trainers
Pascal Fua, EPFL
Mathieu Salzmann, EPFL
Debadeepta Dey, Microsoft Research
Ashish Kapoor, Microsoft Research
Sudipta Sinha, Microsoft Research
Several companies are now launching drones that autonomously follow and film their owners, often by tracking a GPS device they are carrying. This holds the promise to fundamentally change the way in which drones are used, by allowing them to bring back videos of their owners performing activities, such as playing sports, unimpeded by the need to control the drone. In this project, we propose to go one step further and turn the drone into a personal trainer that will not only film, but also analyze the video sequences and provide advice on how to improve performance. For example, a golfer could be followed by such a drone that will detect when the subject swings, and then offer advice on how to improve the motion. Similarly, a skier coming down a slope could be given advice on how to better turn and carve. In short, the drone would replace the GoPro-style action cameras that many people now carry when exercising. Instead of recording what they see, it would film them and augment the resulting sequences with useful advice. To make this solution as lightweight as possible, we will strive to achieve this goal by using the on-board camera as the sole sensor and free the subject from the need to carry a special device that the drone locks onto. This will require:
- Detecting the subject in the video sequences acquired by the drone, so as to keep the subject in the middle of its field of view. This must be done in real-time and integrated into the drone’s control system.
- Recovering the subject’s 3D pose as they move from the drone’s videos. This can be done with a slight delay since the critique only has to be provided once the motion has been performed.
- Providing feedback. In both the golf and ski cases, this would mean quantifying leg, hips, shoulders, and head position during a swing or a turn, offering practical suggestions on how to change them and showing how an expert would have performed the same action.
Revisiting Transactional Computing on Modern Hardware
Rachid Guerraoui, EPFL
Georgios Chatzopoulos, EPFL
Aleksandar Dragojevic, Microsoft Research
Modern hardware trends have changed the way we build systems and applications. Increasing memory (DRAM) capacities at reduced prices make keeping all data in-memory cost-effective, and presents opportunities for high-performance applications, such as in-memory graphs with billions of edges (for example, Facebook’s TAO). Non-Volatile RAM (NVRAM) promises durability in the presence of failures, without the high price of disk accesses. Yet, even with this increase in inexpensive memory, storing the data in the memory of one machine is still not possible for applications that operate on terabytes of data; and systems need to distribute the data and synchronize accesses among machines.
This project proposes the design and building of support for high-level transactions on top of modern hardware platforms, by using SQL. The important question to be answered is whether transactions can get the maximum benefit of these modern networking and hardware capabilities, while offering a significantly easier interface for developers to work with. This project will require both research in the transactional support to be offered, including the operations that can be efficiently supported, as well as research in the execution plans for transactions in this distributed setting.
Fast and Accurate Algorithms for Clustering
Michael Kapralov, EPFL
Ola Svensson, EPFL
Yuval Peres, Microsoft Research
Nikhil Devanur, Microsoft Research
Sebastien Bubeck, Microsoft Research
The task of grouping data according to similarity is a basic computational task, with numerous applications. The right notion of similarity often depends on the application and different measures yield different algorithmic problems.
The goal of this project is to design faster and more accurate algorithms for fundamental clustering problems, such as the k-means problem, correlation clustering, and hierarchical clustering. We propose to perform a granular study of these problems and design algorithms that achieve optimal trade-offs between approximation quality, runtime, and space/communication complexity; making our algorithms well-suited for modern data models such as streaming and MapReduce.
Overviews for projects dating from 2014-2016
Edouard Bugnion, EPFL
Babak Falsafi, EPFL
Dushyanth Narayanan, Microsoft Research
Our primary focus is the study of the computer architectural and system software implications of aggressive scale-out, energy-efficient computing in datacenters.
Datacenter workloads are rapidly evolving from simple data-serving tasks to sophisticated analytics operating over enormous datasets in response to real-time queries. To minimize the response latency, datacenter operators keep the data in memory. As dataset sizes push into the petabyte range, the number of servers required to house them in memory can easily reach into the hundreds or even thousands.
Because of distributed memory, workloads that traverse large data structures (for example, graph data serving) or frequently access disparate pieces of data (for example, key-value stores) must do so over the datacenter network. In today’s commodity-based datacenters, node-to-node communication delays can exceed 100μs . In contrast, accesses to local memory incur delays of around 50ns – a factor of 1000x less.
Our vision proposes Scale-Out NUMA (soNUMA), a programming model, communication protocol, and architectural support for low-latency, distributed, in-memory processing. soNUMA combines an RDMA-inspired programming model layered on top of NUMA fabrics by using a user-level stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA relies on a remote memory controller – a new, architecturally exposed hardware block integrated into the node’s coherence hierarchy.
Our research plan calls for a deeper analysis and prototyping of soNUMA (likely by using FPGA) and the evaluation of complex applications such as key-value stores on the platform. We will also design and evaluate system-level abstractions that take advantage of the platform, to create a cluster-wide socket abstraction that operates at memory speed and provides the foundation for a cluster-wide, fault-resilient single system image.
Authenticated Encryption: Security Notions, Constructions, and Applications
Serge Vaudenay, EPFL
Markulf Kohlweiss, Microsoft Research
For an encryption scheme to be practically useful, it must deliver on two complementary goals: the confidentiality and integrity of encrypted data. Historically, these goals were achieved by combining separate primitives, one to ensure confidentiality and another to guarantee integrity. This approach is neither the most efficient (for instance, it requires processing the input stream at least twice), nor does it protect against implementation errors. To address these concerns, the notion of Authenticated Encryption (AE), which simultaneously achieves confidentiality and integrity, was put forward as a desirable first-class primitive to be exposed by libraries and APIs to the end developer. Providing direct access to AE rather than requiring developers to orchestrate calls to several lower-level functions is seen as a step towards improving the quality of security-critical code.
An indication of both the importance of useable AE and the difficulty of getting it right, are the number of standards that were developed over the years. These specified different methods for AE: the CCM method is specified in IEEE 802.11i, IPsec ESP, and IKEv2; the GCM method is specified in NIST SP 800-38D; the EAX method is specified in ANSI C12.22; and ISO/IEC 19772:2009 defines six methods, including five dedicated AE designs and one generic composition method, namely Encrypt-then-MAC.
Several security issues have recently arisen and been reported in the (mis)use of symmetric key encryption with authentication in practice. As a result, the cryptographic community has initiated the Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR), to boost public discussions towards a better understanding of these issues, and to identify a portfolio of efficient and secure AE schemes.
Our project aims to contribute to the design, analysis, evaluation, and classification of the emerging AE schemes during the CAESAR competition. It has effected many practical security protocols that use AE schemes as indispensable underlying primitives. Our work has broader implications for the theory of AE as an important research area in symmetric-key cryptography.
Towards Resource-Efficient Data Centers
Florin Dinu, EPFL
Sergey Legtchenko, Microsoft Research
Our vision is of resource-efficient datacenters where the compute nodes are fully utilized. We see two challenges to manifesting this vision. The first is the increasing use of hardware heterogeneity in datacenters. Heterogeneity, while both unavoidable and desirable, does not lend itself to today’s systems and algorithms, which inefficiently handle heterogeneity. The second challenge is the aggressive scale-out of datacenters. Scale-out has made it conveniently easy to disregard inefficiencies at the level of individual compute nodes because it has been historically easy to expand to new resources. However, apart from being unnecessarily costly, such scale-out techniques are now becoming impractical due to the size of the datasets. Moreover, scale-out often adds new inefficiencies.
We argue that to meet these challenges, we must start from a thorough understanding of the resource requirements of today’s datacenter jobs. With this understanding, we aim to design new scheduling techniques that efficiently use resources, even in heterogeneous environments. Further, we aim to fundamentally change the way data-parallel processing systems are built and to make efficient compute node resource utilization a cornerstone of their design.
Our first goal is to automatically characterize the pattern of memory requirements of data-parallel jobs. Specifically, we want to go beyond the current practices that are interested only in peak memory usage. To better identify opportunities for efficient memory management, more granular information is necessary.
Our second goal is to use knowledge of the pattern of memory requirements to design informed scheduling algorithms that manage memory efficiently.
The third goal of the project is to design data-parallel processing systems that are efficient in terms of managing memory, not only by understanding task memory requirements, but also by shaping those memory requirements.
ETH Zurich projects
Overviews for projects dating from 2017-2018
Data Science with FPGAs in the Datacenter
Gustavo Alonso, ETH Zurich
Ken Eguro, Microsoft Research
While in the first phase of the project we explored the efficient implementation of data processing operators in FPGAs, as well as the architectural issues involved in the integration of FPGAs as co-processors in commodity servers, we are now focusing on architectural aspects of in-network data processing. This is due to the growing gap between bandwidth and very low latencies that modern networks support, and the overhead of ingress and egress from VMs and applications running on conventional CPUs. The first goal is to explore the type of problems and algorithms that can be best run as the data flows through the network, so as to be able to exploit the bare wire speed and allow off-loading of expensive computations to the FPGA. The second, and equally important goal, is to explore the best way to operate FPGA-based accelerators when directly connected to the network and operating independently from the software part of the application. In terms of applications, the focus will remain on data processing (relational, No-SQL, data warehouses, etc.), with the intention of starting to move towards machine learning algorithms at the end of the two-year project. On the network side, the project will work on developing networking protocols suitable to this new configuration and how to combine the network stack with the data processing stack.
Human-Centric Flight II: End-user Design of High-level Robotic Behavior
Otmar Hilliges, ETH Zurich
Marc Pollefeys, Microsoft and ETH Zurich
Micro-aerial vehicles (MAVs) have been made accessible to end-users via the emergence of simple-to-use hardware and programmable software platforms. Consequently, this has resulted in a surge in consumer and research interest. Clearly there is a desire to use such platforms in a variety of application scenarios, but manually flying quadcopters remains a surprisingly hard task even for experts. More importantly, state-of-the-art technologies offer only very limited support for users who want to employ MAVs to reach a certain high-level goal. This is perhaps best illustrated by the currently most successful application area – that of aerial videography. While manual flight is difficult, piloting and controlling a camera simultaneously is practically impossible. An alternative to manual control is offered via waypoint-based control of MAVs, which shields novices from the underlying complexities. However, this simplicity comes at the cost of flexibility. Existing flight-planning tools are not designed with high-level user goals in mind.
Building on our prior work, we propose an alternative approach to robotic motion planning. The key idea is to let the user work in the solution space. Instead of defining trajectories, the user would define what the resulting output should be (for example, shot composition, transitions, area to reconstruct). We propose an optimization-based approach that takes such high-level goals as input and automatically generates the trajectories and control inputs for a gimbal-mounted camera. We call this solution-space driven, inverse kinematic motion planning. Defining the problem directly in the solution space removes several layers of indirection and allows users to operate in a more natural way, focusing only on the application-specific goals and the quality of the final result, whereas the control aspects are entirely hidden.
Tractable by Design
Thomas Hofmann, ETH Zurich
Aurélien Lucchi, ETH Zurich
Sebastian Nowozin, Microsoft Research
The past decade has seen a growth of big data and machine learning systems. Probabilistic models of data are theoretically well understood and, in principle, provide an optimal approach to inference and learning from data. However, for richly structured data domains, such as natural language and images, probabilistic models are often computationally intractable and/or have to make strong conditional independence assumptions to retain computational, as well as statistical, efficiency. As a consequence, they are often inferior in predictive performance, when compared to current state-of-the-art deep learning approaches. It is a natural question to ask, whether one can combine the benefits of deep learning with those of probabilistic models. The major conceptual challenge is to define deep models that are generative, i.e. that can be thought of as models of the underlying data-generating mechanism.
We thus propose to leverage and extend recent advances in generative neural networks to build rich probabilistic models for structured domains, such as text and images. The extension of efficient probabilistic neural models will allow us to represent complex and multimodal uncertainty efficiently. To demonstrate the usefulness of the developed probabilistic neural models, we plan to apply them to challenging multimodal applications, such as creating textual descriptions for images or database records.
Enabling Practical, Efficient, and Large-Scale Computation Near Data to Improve the Performance and Efficiency of Datacenter and Consumer Systems
Onur Mutlu, ETH Zurich
Luca Benini, ETH Zurich
Derek Chiou, Microsoft
Today’s systems are overwhelmingly designed to move data to computation. This design choice goes directly against key trends in systems and technology that cause performance, scalability, and energy bottlenecks:
- Data access from memory is a key bottleneck as applications become more data intensive and memory bandwidth and energy do not scale well.
- Energy consumption is a key constraint, especially in mobile and server systems.
- Data movement is very costly in terms of bandwidth, energy and latency, much more so than computation.
Our goal is to comprehensively examine the premise of adaptively performing computation near where the data resides, when it makes sense to do so, in an implementable manner and considering multiple new memory technologies, including 3D-stacked memory and non-volatile memory (NVM). We will examine practical hardware substrates and software interfaces to accelerate key computational primitives of modern data-intensive applications in memory, runtime, and software techniques that can take advantage of such substrates and interfaces. Our special focus will be on key data-intensive applications, including deep learning, neural networks, graph processing, bioinformatics (DNA sequence analysis and assembly), and in-memory data stores. Our approach is software/hardware cooperative, breaking the barriers between the two and melding applications, systems, and hardware substrates for extremely efficient execution, while still providing efficient interfaces to the software programmer.
Overviews for projects dating from 2014-2016
Human-Centric Flight: Micro-Aerial Vehicles (MAVs) for Interaction, Videography, and 3D Reconstruction
Otmar Hilliges, ETH Zurich
Marc Pollefeys, ETH Zurich
Shahram Izadi, Microsoft Research
In recent years, robotics research has made tremendous progress and it is becoming conceivable that robots will be as ubiquitous and irreplaceable in our daily lives as they are within industrial settings. Continued improvements, in terms of mechatronics and control aspects, coupled with continued advances in consumer electronics, have made robots ever smaller, autonomous, and agile.
One area of recent advances in robotics is the notion of micro-aerial vehicles (MAVs) [14, 16]. These are small, flying robots that are very agile, can operate in a 3D space, indoors and outdoors, and can carry small payloads — including input and output devices — and can navigate difficult environments, such as stairs, more easily than terrestrial robots; and hence can reach locations that no other robot or indeed humans can reach.
Surprisingly, to date there is little research on such flying robots in an interactive context or on MAVs operating in near proximity to humans. In our project, we explore the opportunities that arise from aerial robots that operate in close proximity to and in collaboration with a human user. In particular, we are interested in developing a robotic platform in which a) the robot is aware of the human user and can navigate relative to the user; b) the robot can recognize various gestures from afar, as well as receive direct, physical manipulations; c) the robot can carry small payloads — in particular input and output devices such as additional cameras or projectors.
Finally, we are developing novel algorithms to track and recognize user input, by using the onboard cameras, in real-time and with very low-latency, to build on the now substantial body of research on gestural and natural interfaces. Gesture recognition can be used for MAV control (for example, controlling the camera) or to interact with virtual content.
Software-Defined Networks: Algorithms and Mechanisms
Roger Wattenhofer, ETH Zurich
Ratul Mahajan, Microsoft Research
The Internet is designed as a robust service to ensure that we can use it with selfish participants present. As such, a loss in total performance must be accepted. However, if a whole wide-area network (WAN) was controlled by a single entity, why should one use the very techniques designed for the Internet? Large providers such as Microsoft, Amazon, or Google operate their own WANs, which cost them hundreds of millions of dollars per year; yet even their busier links average only 40–60 percent utilization.
This gives rise to Software Defined Networks (SDNs), which allow the separation of the data and the control plane in a network. A centralized controller can install and update rules all over the WAN, to optimize its goals.
Despite SDNs receiving a lot of attention in both theory and practice, many questions are still unanswered. Even though the control of the network is centralized, distributing the updates does not happen instantaneously. Numerous problems can occur, such as the dropping of packets, generation of loops, breaking the memory/bandwidth limit of switches/links, and missing packet coherence. These problems must be solved before SDNs can be broadly deployed.
This research project sheds more light on these fundamental issues of SDNs and how they can be tackled. In parallel, we look at SDNs from a game-theoretic perspective.
Efficient Data Processing Through Massive Parallelism and FPGA-Based Acceleration
Gustavo Alonso, ETH Zurich
Ken Eguro, Microsoft Research
One of the biggest challenges for software these days is to adapt to the rapid changes in hardware and processor architecture. On the one hand, extracting performance from modern hardware requires dealing with increasing levels of parallelism. On the other hand, the wide variety of architectural possibilities and multiplicity of processor types raise many questions in terms of the optimal platform for deploying applications.
In this project we will explore the efficient implementation of data processing operators in FPGAs, as well as the architectural issues involved in the integration of FPGAs as co-processors in commodity servers. The target application is big data and data processing engines (relational, No-SQL, data warehouses, etc.). Through this line of work, the project aims at exploring architectures that will result in computing nodes with a smaller energy consumption and physical size, but capable of providing a performance boost to applications for big data. FPGAs should be seen here not as a goal in themselves, but as an enabling platform for the exploration of different architectures and levels of parallelism that will allow us to bypass the inherent restriction of conventional processors.
On the practical side, the project will focus on both the use of FPGAs as co-processors inside existing engines, as well as on developing proof-of-concept implementations of data processing engines entirely implemented in FPGAs. In this area, the project complements very well with ongoing efforts at Microsoft Research around Cipherbase, a trusted computing system based on SQL server deployments in the cloud. On the conceptual side, the project will explore the development of data structures and algorithms capable of exploiting the massive parallelism available in FPGAs, with a view to gaining much needed insights on how to adapt existing data processing systems to multi- and many-core architectures. Here, we expect to gain insights on how to redesign both standard relational data operators, as well as data mining and machine learning operators, to better take advantage of the increasing amounts of parallelism available in future processors.
ARRID: Availability and Reliability as a Resource for Large-Scale In-Memory Databases on Datacenter Computers
Torsten Hoefler, ETH Zurich
Miguel Castro, Microsoft Research
Disk-backed in-memory key/value stores are gaining significance as many industries are moving toward big data analytics. Storage space and query time requirements are challenging, since the analysis has to be performed at the lowest cost to be useful from a business perspective. Despite those cost constraints, today’s systems are heavily overprovisioned when it comes to resiliency. The undifferentiated three-copy approach leads to a potential waste of bandwidth and storage resources, which then makes the overall system less efficient or more expensive. We propose to revisit currently used resiliency schemes, with the help of analytical hardware failure models. We will utilize those models to capture the exact tradeoff between the overhead due to replication and the exact resiliency requirements that are defined in a contract. Our key idea is to model reliability as an explicit resource that the user allocates consciously. In previous work, we have been able to speed-up scientific computing applications, as well as a distributed hashtable, on several hundred-thousand cores by more than 20 percent, with the use of advanced RDMA programming techniques. We have also demonstrated low-cost resiliency schemes based on erasure coding for RDMA environments. In addition, we propose to apply our experience with large-scale RDMA programming to the design of in-memory databases, a problem very similar to distributed hashtables. To make reliability explicit, we plan to extend the key value store with explicit reliability attributes that allow the user to specify reliability and availability requirements for each key (or group of keys). Our work may change the perspective in datacenter resiliency. Defining fine-grained, per-object resiliency levels and tuning them to the exact environment may provide large cost benefits and impact industry. For example, changing the standard three-replica scheme to erasure coding can easily save 30 percent of storage expenses.
Blogs & podcasts
Microsoft Research Podcast | April 10, 2019
Microsoft Switzerland | February 5, 2019
Microsoft continues to invest in research cooperation with ETH and EPFL, thereby strengthening Switzerland’s innovation power
Microsoft Switzerland | November 1, 2018
Microsoft Switzerland | October 29, 2018
Microsoft Research Blog | December 4, 2017
Microsoft Research Blog | February 21, 2017
Microsoft Research Blog | February 5, 2014
Microsoft Research Blog | February 5, 2014
In the news
Man and Machine – Panel discussion at WEF 2019
ETH Zürich | February 12, 2019
Microsoft CEO Satya Nadella at ETH Zurich
Startup Ticker | November 1, 2018
ETH and Microsoft: Hunting for talent
ETH News | November 1, 2018
Microsoft expands partnership with ETH Zurich
Inside IT & Inside Channels | November 1, 2018
ETH seeks to benefit more strongly from partnership with Microsoft
Greater Zurich Area | November 2, 2018
Microsoft and ETH are chasing talent
Netzwoche | November 2, 2018
Microsoft CEO Satya Nadella visits ETH Zurich
Computerworld | November 2, 2018
Microsoft extends cooperation with ETH, EPFL, partners with Mixed Reality & AI Zurich Lab
Telecompaper | November 2, 2018