Hardware verification on FPGAs runs more than three orders of magnitude faster than software simulations, however with much lower visibility into the design under test. To expedite the task of debugging and specification verification, we propose a tool framework that automates many tedious aspects of the process. We provide tools to mine assertions either from simulation or hardware traces, to generate assertion checking engines implemented as efficient Verilog state machines, to rewrite the user’s Verilog code inserting probes to the relevant signals, and to dynamically vary the operating clock frequency of the design under test. During implementation, we ensure that the layout of the original design is preserved as much as possible by automatically generating placement constraints, and thereby minimizing the uncertainty introduced by other on-chip debugging techniques.