Globally Optimized Robust System Design

August 29, 2008
Subhasish Mitra | Stanford University

Future system design methodologies must accept the fact that the underlying hardware will be imperfect, and enable design of robust systems that are resilient to such imperfections. This talk will describe enabling tools and technologies for building such systems. Three techniques that can enable a sea change in robust system design are: 1. Built-In Soft Error Resilience (BISER), 2. Circuit Failure Prediction, and 3. Concurrent Autonomous Self-Test and Self-Diagnosis. These techniques span multiple abstraction layers (circuit, architecture, virtualization and application), and enable global optimization across these layers. The applicability of such techniques in overcoming the growing challenge of post-Silicon validation will also be discussed.

Speaker Details

Subhasish Mitra is an Assistant Professor in the Departments of Electrical Engineering and Computer Science of Stanford University where he leads the Stanford Robust Systems Group. His research interests include robust system design, VLSI design, CAD and test, fault-tolerant computing, and design for emerging nanotechnologies. Prior to joining Stanford, he was a Principal Engineer at Intel. He received Ph.D. in Electrical Engineering from Stanford.Prof. Mitra has co-authored 100+ technical papers, and his robust system design techniques have seen wide-spread proliferation in the semiconductor industry. His X-Compact technique for test compression is used by 50+ Intel products, and is supported by major CAD tools. His work on imperfection-immune circuits using carbon nanotubes, jointly with his students and collaborators, has been highlighted as a “significant breakthrough” by the Semiconductor Research Corporation, MIT Technology Review, EE Times, and many others. His major honors include the NSF CAREER Award, Terman Fellowship, IEEE CAS Donald O. Pederson Award (IEEE Trans. CAD Best Paper Award), ACM SIGDA Outstanding New Faculty Award, Design Automation Conference (DAC) Best Paper Award, Intel Divisional Recognition Award “for a Breakthrough Soft Error Protection Technology,” and the Intel Achievement Award, Intel’s highest corporate honor, “for a breakthrough test compression technology.”