The Project Catapult Academic Program allows researchers worldwide to investigate new ways of using interconnected FPGAs as computational accelerators—a unique opportunity to access custom data center systems for high-demand research. Using the low-latency Catapult system opens up opportunities to create innovative applications and run high-demand research applications—such as machine learning and deep learning algorithms—at previously unavailable efficiencies and scale.
The Project Catapult Academic Program is run in collaboration with the Texas Advanced Computing Center (TACC) at The University of Texas at Austin, and Intel. It provides researchers with free access to Microsoft Catapult FPGA systems located at TACC, including 384 Catapult nodes at TACC, and a Catapult shell development kit, tools, and examples for researchers to develop their own FPGA applications to run on the Catapult FAbRIC platform.
Researchers can request access to the Microsoft Project Catapult system at the TACC by following the instructions on the Apply tab and sending a one-page proposal to firstname.lastname@example.org.
General questions regarding Project Catapult Academic Program may be sent to email@example.com
Keep updated via the Catapult mailing list
- Request a TACC account. Your account has to be activated by signing in to your TACC account at least once.
- Create an Altera account. Enter your university name into the “Company Name” field of the myAltera account registration form.
- After you have these two accounts, please forward the account confirmation emails from your university email address to firstname.lastname@example.org, along with:
- Your one-page proposal outlining the research project, including:
- Full legal name
- Country of citizenship
- Current residential address
- University name
- Department name
- In addition, please include the following license statement in your email:
All of the code that I will pass through FAbRIC CAD tools (such as Verilog files, Bluespec files, etc.) and the files needed to process that code (such as Makefiles) is either already open source (GPL version 2 or above, BSD, or MIT licenses) or I have the right to make it open source and am hereby making all of the code that I pass through FAbRIC CAD tools open source by one of those licenses. I will provide access to my source code to the CAD tool vendors and the FAbRIC administrators immediately. The simplest way to do that is to provide a repository account to the FAbRIC administrators. By default, the CAD tool vendors and/or the FAbRIC administrators agree not to publish the code publicly for at least 12 months.
I acknowledge that the tools, servers, and FPGAs are potentially subject to export controls under U.S. and other applicable government laws and regulations. I will comply with these laws and regulations and agree to obtain all required government authorizations.
I acknowledge that my access to and use of the Microsoft Project Catapult Academic Shell and Driver and related hardware provided by Microsoft is governed by, and subject to, the terms and conditions of the Microsoft Research License Agreement for the Microsoft Project Catapult Academic Shell and Driver. By accessing or using Microsoft Project Catapult materials, I represent and warrant that I have read the agreement, and I agree to be bound by it.
The system consists of 384 2-socket Intel Xeon-based nodes, each with 64 GB of RAM and an Altera Stratix V FPGA with 8 GB of local DDR3 SDRAM. FPGAs communicate to their host CPUs via a PCIe Gen3 x8 connection, providing 8 GB/s guaranteed-not-to-exceed bandwidth, and each FPGA can read and write data stored on its host node using this connection.
The FPGAs are connected to one another via a dedicated network using high-speed serial links. This network, called CatNet (Catapult Network), forms a two-dimensional torus within a pod of 48 servers and provides low-latency communication between neighboring FPGAs. This design supports the use of multiple FPGAs to solve a single problem while adding resilience to server and FPGA failures.
- Two Xeon E5-2450, 2.1 GHz, 8-core, 20 MB Cache, 95W
- 64 GB of RAM
- Four 2 TB 7.2k 3G SATA 3.5″; two 480 GB 6G Micron SATA SSD 2.5
- Intel 82599 10GbE Mezz Card
- Altera Stratix V FPGA Card
- Operating system: Windows Server 2012
At this year’s Supercomputing 2015 Conference in Austin, Texas, Microsoft is announcing the availability of Project Catapult clusters to academic researchers through the Texas Advanced Computing Center (TACC) at The University of Texas at Austin. Project Catapult, a Microsoft research venture, offers a groundbreaking way to vastly improve the performance and energy efficiency of datacenter workloads.
November 2015 | Microsoft Research Blog
Operating a datacenter at web scale requires managing many conflicting requirements. The ability to deliver computation at a high level and speed is a given, but because of the demands such a facility must meet, a datacenter also needs flexibility. Additionally, it must be efficient in its use of power, keeping costs as low as possible. Addressing often conflicting goals is a challenge, leading datacenter providers to seek constant performance…
June 2014 | Microsoft Research Blog
The high-level architecture of datacenter servers has been generally stable for many years, based on some combination of CPUs, DRAM, Ethernet, and disks (with solid-state drives a more recent addition). While the capacities and speeds of the components—and the datacenter scale—have grown, the basic server architecture has evolved slowly.
February 2015 | Microsoft Research Blog
2017 Catapult Academic Tutorial
Over the course of 4 weeks, beginning on October 13, we will be presenting a series of online tutorial sessions to introduce and provide examples of the work that is possible in the Catapult Academic environment.
Altera/Intel Online FPGA Training
Altera has available a full set of online courses on the fundamentals of FPGA programming. These courses are available at the links below.
If you plan on taking advantage of our tutorial, we do recommend taking in, at least, the Quartus training available in the Intel FPGA Fundamentals Part 1 curriculum.
Intel FPGA Fundamentals Part 1
Intel FPGA Fundamentals Part 2