Leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. While there are several process technology and circuit-level solutions to reduce leakage in processors, the research on reducing leakage at the microarchitecture and compiler stage is still nascent. In this talk, I will present some techniques that will help reduce leakage in processors fabricated in sub nanometer technologies.