Compiler and Microarchitectural Techniques for Leakage Power Reduction


September 14, 2007


Aviral Shrivastava and Sarma Vrudhula


Arizona State University


Leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. While there are several process technology and circuit-level solutions to reduce leakage in processors, the research on reducing leakage at the microarchitecture and compiler stage is still nascent. In this talk, I will present some techniques that will help reduce leakage in processors fabricated in sub nanometer technologies.


Aviral Shrivastava and Sarma Vrudhula

Aviral Shrivastava is an Assistant Professor in the Department of Computer Science and Engineering, at the Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML). This lab brings together researchers to concentrate on cutting-edge issues at the compiler and processor microarchitecture boundary.

Dr. Shrivastava received his Ph.D. and Masters in Computer Science and Engineering from University of California, Irvine. His bachelor’s degree is also in Computer Science and Engineering from Indian Institute of Technology, Delhi. His areas of interest lie at the intersection of Compilers, Computer Architecture, and VLSI CAD; with a particular focus at the interface of embedded processor architectures and their compilers. He has developed several compiler techniques to exploit microarchitectural features and optimize power, performance, code size, reliability, etc.